hp93000,timing,0.1
EQSP TIM,WVT,#9000077686
#
# Date     : 12:30:49 Wednesday August 3, 2005
# File     : EM8634_revA_v1_00.timing (93k equation timing file)
#
# History  : r1.0  10/18/05   Original
#            r1.1  03/20/06   Add xos setup timing (1.45V at 10MHz) for skip serial flash
#                            check.
#            r1.2  04/16/06   same as r1.1
#            r1.21 04/25/06   Change scanx3 closk to 0.30-0.85 (from 0.35-0.85)
#            r1.21 04/25/06   Change scanx3 closk to 0.30-0.85 (from 0.35-0.85)
#
#            r2.0  10/2006    Release r2.0
#            r2.1  11/18/06   added drambist_VO and atspeed_bist
#            r3.0  12/06/06   - added atspeed_bist_5us (5us of RCLK1_XTAL_IN running at 40MHz)
#                             - Remove drambist_VO and at_speed_bist. For at_speed_bist, use 
#                               at_speed_bist_5us instead. (removed following wavetable & equation set)
#                               - WAVETBL "dram_bist_VO" # wave table definition
#                                 WAVETBL "atspeed_bist" # wave table definition
#                                 EQNSET 10 "dram_bist_VO"
#                                 EQNSET 11 "atspeed_bist"
#
#            r3.1  02/16/07   - added display_func timing (Horizontal Noise)
#
#            r3.1x 03/10/07   - Mask out PCI* signals in dram_func test
#                  03/15/07   - modify RCLK1_XTAL_IN to RZ (as RCLK0_IN)
#
# RevC       1.00  04/07/07   - Copied from revB r3.1x.timing 
#                             - added dram_func timing 
#
# RevC       1.00  04/12/07   - add serial_flash_x2 timing for x2 mode
#
# RevC       1.00  08/07/07   - Modified PB_AD[*] r1 from 1.2 to 1.7 * Tcyc
#                               for EQNSET atspeed...                      
#
# RevC       1.10  12/08/07   - Same as r1.0, rename to 1.1 to keep up with the rev.
#
##########################################################
#    scan Timing Wave Table                              #
##########################################################
WAVETBL "scan" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#########################################
###   WAVETABLE FOR NON-SCAN PINS     ###
#########################################


# Timeplate Input  Group 0

PINS DRAM0_DQS[3] DRAM0_DQS[2] DRAM0_DQS[1] DRAM0_DQS[0] DRAM1_DQS[3] DRAM1_DQS[2] DRAM1_DQS[1] DRAM1_DQS[0] TS0_IN_CLK TS0_IN_VLD TS0_IN_SYNC TS0_IN_D[7] TS0_IN_D[6] TS0_IN_D[4] TS0_IN_D[3] TS0_IN_D[2] TS0_IN_D[0] TS1_IN_CLK TS1_IN_VLD TS1_IN_SYNC TS1_IN_D[7] TS1_IN_D[6] TS1_IN_D[5] TS1_IN_D[4] TS1_IN_D[3] TS1_IN_D[2] TS1_IN_D[0] TDMX_GPIO[1] TDMX_GPIO[0] SI0_SPDIF SI0_DATA SI0_CLK SI0_LRCLK SI1_SPDIF SI1_DATA SI1_CLK SI1_LRCLK HDMI_MSEN HDMI_HPD VI0_CLK VI0_P[31] VI0_P[30] VI0_P[29] VI0_P[28] VI0_P[27] VI0_P[26] VI0_P[25] VI0_P[24] VI0_P[23] VI0_P[22] VI0_P[21] VI0_P[20] VI0_P[19] VI0_P[18] VI0_P[17] VI0_P[16] VI0_P[15] VI0_P[14] VI0_P[13] VI0_P[12] VI0_P[11] VI0_P[10] VI0_P[9] VI0_P[8] VI0_P[7] VI0_P[6] VI0_P[5] VI0_P[4] VI0_P[3] VI0_P[2] VI0_P[1] VI0_P[0] VI0_VLD VI0_HS VI0_VS VI1_CLK VI1_P[7] VI1_P[6] VI1_P[5] VI1_P[4] VI1_P[3] VI1_P[2] VI1_P[1] VI1_P[0] VI1_VLD VI1_HS VI1_VS VI2_CLK VI2_VLD VI2_HS VI2_VS VO0_HS VO0_VS PCI_REQB[3] PCI_REQB[2] PCI_REQB[1] PCI_REQB[0] PB_IORDY PB_DMARQ IDE_IORDY IDE_INTRQ IDE_DMARQ IDE_NPCBLID JTAG_UART RTC_XTAL_IN RTC_TEST RTC_XTAL_DISC RTC_CLK_IN XTAL_IN XTAL_BUF XTAL_DISC RCLK1_XTAL_IN TEST 
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

# Timeplate Input  Group 1

PINS TS0_IN_D[5] TS0_IN_D[1] TS1_IN_D[1] PCI_CLK VCXO0_IN VCXO1_IN RCLK0_IN GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] 
  4   " d1:F00        "  0
  5   " d1:F10 d3:F00 "  1
brk   ""

# Timeplate Input  Group 2

PINS RESETB 
  4   " d1:F00 d3:F10 "  0
  5   " d1:F10        "  1
brk   ""

# Timeplate Output Group 0

PINS DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[13] DRAM0_A[12] DRAM0_A[11] DRAM0_A[10] DRAM0_A[9] DRAM0_A[8] DRAM0_A[7] DRAM0_A[6] DRAM0_A[5] DRAM0_A[4] DRAM0_A[3] DRAM0_A[2] DRAM0_A[1] DRAM0_A[0] DRAM0_BA[1] DRAM0_BA[0] DRAM0_DM[3] DRAM0_DM[2] DRAM0_DM[1] DRAM0_DM[0] DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[13] DRAM1_A[12] DRAM1_A[11] DRAM1_A[10] DRAM1_A[9] DRAM1_A[8] DRAM1_A[7] DRAM1_A[6] DRAM1_A[5] DRAM1_A[4] DRAM1_A[3] DRAM1_A[2] DRAM1_A[1] DRAM1_A[0] DRAM1_BA[1] DRAM1_BA[0] DRAM1_DM[3] DRAM1_DM[2] DRAM1_DM[1] DRAM1_DM[0] SO0_ACLK SO0_CLK SO0_LRCLK SO0_DATA1 SO0_DATA2 SO0_DATA3 SO0_DATA4 SO0_DATA5 SO0_SPDIF SO1_ACLK SO1_CLK SO1_LRCLK SO1_DATA1 SO1_DATA2 SO1_DATA3 SO1_DATA4 SO1_DATA5 SO1_SPDIF HDMI_PDB VO0_CLK VO0_P[23] VO0_P[22] VO0_P[21] VO0_P[20] VO0_P[19] VO0_P[18] VO0_P[17] VO0_P[16] VO0_P[15] VO0_P[14] VO0_P[13] VO0_P[12] VO0_P[11] VO0_P[10] VO0_P[9] VO0_P[8] VO0_P[7] VO0_P[6] VO0_P[5] VO0_P[4] VO0_P[3] VO0_P[2] VO0_P[1] VO0_P[0] VO0_VLD PCI_AD[31] PCI_AD[30] PCI_CBEB[3] PCI_CBEB[2] PCI_CBEB[1] PCI_CBEB[0] PCI_PAR PCI_FRAMEB PCI_TRDYB PCI_IRDYB PCI_STOPB PCI_DEVSELB PCI_INTAB PB_A[24] PB_A[23] PB_A[22] PB_A[21] PB_A[20] PB_A[19] PB_A[18] PB_A[17] PB_A[16] PB_CSB[3] PB_CSB[2] PB_CSB[1] PB_CSB[0] PB_RDB PB_WRB PB_ALE PB_DMACKB PB_DIRB IDE_HIORN IDE_HIOWN IDE_DACKN IDE_HA[2] IDE_HA[1] IDE_HA[0] IDE_CS0N IDE_CS1N IDE_HD[15] IDE_HD[14] IDE_HD[13] IDE_HD[12] IDE_HD[11] IDE_HD[10] IDE_HD[9] IDE_HD[8] IDE_HD[7] IDE_HD[6] IDE_HD[5] IDE_HD[4] IDE_HD[3] IDE_HD[2] IDE_HD[1] IDE_HD[0] ETH_TXCLK ETH_TX_EN ETH_TXD[3] ETH_TXD[2] ETH_TXD[1] ETH_TXD[0] ETH_RXCLK ETH_RX_DV ETH_RX_ER ETH_RXD[3] ETH_RXD[2] ETH_RXD[1] ETH_RXD[0] ETH_CRS ETH_COL ETH_MDC ETH_MDIO ETH_MDINTB ETH_GPIO[15] ETH_GPIO[14] ETH_GPIO[13] ETH_GPIO[12] ETH_GPIO[11] ETH_GPIO[10] ETH_GPIO[9] ETH_GPIO[8] ETH_GPIO[7] ETH_GPIO[6] ETH_GPIO[5] ETH_GPIO[4] ETH_GPIO[3] ETH_GPIO[2] ETH_GPIO[1] ETH_GPIO[0] UART0_RX UART0_CTS UART0_DSR UART0_DCD UART0_TX UART0_RTS UART0_DTR UART1_RX UART1_CTS UART1_DSR UART1_DCD UART1_TX UART1_RTS UART1_DTR SCARD_RST SCARD_CLK SCARD_FCB SCARD_IO SCARD_CTL[2] SCARD_CTL[1] SCARD_CTL[0] RTC_XTAL_OUT RTC_RING RTC_CLK_OUT XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT GPIO[13] GPIO[12] GPIO[11] GPIO[10] GPIO[9] GPIO[8] GPIO[7] GPIO[6] 
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

# Timeplate InOut  Group 0

PINS DRAM0_DQ[31] DRAM0_DQ[30] DRAM0_DQ[29] DRAM0_DQ[28] DRAM0_DQ[27] DRAM0_DQ[26] DRAM0_DQ[25] DRAM0_DQ[24] DRAM0_DQ[23] DRAM0_DQ[22] DRAM0_DQ[21] DRAM0_DQ[20] DRAM0_DQ[19] DRAM0_DQ[18] DRAM0_DQ[17] DRAM0_DQ[16] DRAM0_DQ[15] DRAM0_DQ[14] DRAM0_DQ[13] DRAM0_DQ[12] DRAM0_DQ[11] DRAM0_DQ[10] DRAM0_DQ[9] DRAM0_DQ[8] DRAM0_DQ[7] DRAM0_DQ[6] DRAM0_DQ[5] DRAM0_DQ[4] DRAM0_DQ[3] DRAM0_DQ[2] DRAM0_DQ[1] DRAM0_DQ[0] DRAM1_DQ[31] DRAM1_DQ[30] DRAM1_DQ[29] DRAM1_DQ[28] DRAM1_DQ[27] DRAM1_DQ[26] DRAM1_DQ[25] DRAM1_DQ[24] DRAM1_DQ[23] DRAM1_DQ[22] DRAM1_DQ[21] DRAM1_DQ[20] DRAM1_DQ[19] DRAM1_DQ[18] DRAM1_DQ[17] DRAM1_DQ[16] DRAM1_DQ[15] DRAM1_DQ[14] DRAM1_DQ[13] DRAM1_DQ[12] DRAM1_DQ[11] DRAM1_DQ[10] DRAM1_DQ[9] DRAM1_DQ[8] DRAM1_DQ[7] DRAM1_DQ[6] DRAM1_DQ[5] DRAM1_DQ[4] DRAM1_DQ[3] DRAM1_DQ[2] DRAM1_DQ[1] DRAM1_DQ[0] HDMI_DSCL HDMI_DSDA PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_IDSEL[0] PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] 
  4   " d1:F00 r1:X "  0
  5   " d1:F10 r1:X "  1
  6   " d1:F0Z r1:X "  X
  7   " d1:F0Z r1:L "  L
  8   " d1:F0Z r1:H "  H
  9   " d1:F0Z r1:X "  Z
brk   ""

#########################################
###   WAVETABLE FOR SCAN PINS         ###
#########################################


PINS PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] GPIO[15] GPIO[14]
  0   " r1:L "  l
  1   " r1:H "  h
  2   " r1:X "  x
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS PB_AD[15] PB_AD[14] PB_AD[13] PB_AD[12] PB_AD[11] PB_AD[10] PB_AD[9] PB_AD[8] PB_AD[7] PB_AD[6] PB_AD[5] PB_AD[4] PB_AD[3] PB_AD[2] PB_AD[1] PB_AD[0] PB_A[15] PB_A[14] PB_A[13] PB_A[12] PB_A[11] PB_A[10] PB_A[9] PB_A[8] PB_A[7] PB_A[6] PB_A[5] PB_A[4] PB_A[3] PB_A[2] PB_A[1] PB_A[0]
  0   " d1:F00 "  d
  1   " d1:F10 "  u
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


###################################################
#####  050820    mask                         #####
###################################################
#PINS  PCI_AD[12] 
#  0   " r1:X "  l
#  1   " r1:X "  h
#  2   " r1:X "  x
#  6   " r1:X "  X
#  7   " r1:X "  L
#  8   " r1:X "  H
#  9   " r1:X "  Z

PINS RCLK1_XTAL_OUT RCLK3_OUT  
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

##########################################################
#    scan x3 Timing Wave Table                           #
##########################################################
WAVETBL "scanx3" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS DRAM0_VREFSSTL1
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS DRAM0_VREFSSTL23
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS DRAM1_VREFSSTL0
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS DRAM1_VREFSSTL1
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS DRAM1_VREFSSTL23
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS USB20_XI
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

PINS USB20_XO
  2   " r1:X "  X
  3   " r1:L "  L
  4   " r1:H "  H
  7   " r2:X r3:X r4:X "  XXX
  8   " r2:L r3:L r4:L "  LLL
  9   " r2:H r3:H r4:H "  HHH

PINS WDA_SYNC
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

#########################################
###   WAVETABLE FOR NON-SCAN PINS     ###
#########################################


# Timplate Input  Group 0

PINS DRAM0_DQS[3] DRAM0_DQS[2] DRAM0_DQS[1] DRAM0_DQS[0] DRAM1_DQS[3] DRAM1_DQS[2] DRAM1_DQS[1] DRAM1_DQS[0] TS0_IN_CLK TS0_IN_VLD TS0_IN_SYNC TS0_IN_D[7] TS0_IN_D[6] TS0_IN_D[4] TS0_IN_D[3] TS0_IN_D[2] TS0_IN_D[0] TS1_IN_CLK TS1_IN_VLD TS1_IN_SYNC TS1_IN_D[7] TS1_IN_D[6] TS1_IN_D[5] TS1_IN_D[4] TS1_IN_D[3] TS1_IN_D[2] TS1_IN_D[0] TDMX_GPIO[1] TDMX_GPIO[0] SI0_SPDIF SI0_DATA SI0_CLK SI0_LRCLK SI1_SPDIF SI1_DATA SI1_CLK SI1_LRCLK HDMI_MSEN HDMI_HPD VI0_CLK VI0_P[31] VI0_P[30] VI0_P[29] VI0_P[28] VI0_P[27] VI0_P[26] VI0_P[25] VI0_P[24] VI0_P[23] VI0_P[22] VI0_P[21] VI0_P[20] VI0_P[19] VI0_P[18] VI0_P[17] VI0_P[16] VI0_P[15] VI0_P[14] VI0_P[13] VI0_P[12] VI0_P[11] VI0_P[10] VI0_P[9] VI0_P[8] VI0_P[7] VI0_P[6] VI0_P[5] VI0_P[4] VI0_P[3] VI0_P[2] VI0_P[1] VI0_P[0] VI0_VLD VI0_HS VI0_VS VI1_CLK VI1_P[7] VI1_P[6] VI1_P[5] VI1_P[4] VI1_P[3] VI1_P[2] VI1_P[1] VI1_P[0] VI1_VLD VI1_HS VI1_VS VI2_CLK VI2_VLD VI2_HS VI2_VS VO0_HS VO0_VS PCI_REQB[3] PCI_REQB[2] PCI_REQB[1] PCI_REQB[0] PB_IORDY PB_DMARQ IDE_IORDY IDE_INTRQ IDE_DMARQ IDE_NPCBLID JTAG_UART RTC_XTAL_IN RTC_TEST RTC_XTAL_DISC RTC_CLK_IN XTAL_IN XTAL_BUF XTAL_DISC RCLK1_XTAL_IN TEST 
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

# Timplate Input  Group 1

PINS TS0_IN_D[5] TS0_IN_D[1] TS1_IN_D[1] PCI_CLK VCXO0_IN VCXO1_IN RCLK0_IN GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] 
  0   " d1:F00 d3:F00 "  0
  1   " d1:F10 d3:F00 "  1
  5   " d4:F00 d2:F00 d5:F00 d7:F00 d8:F00 d6:F00 "  000
  6   " d4:F10 d2:F00 d5:F10 d7:F00 d8:F10 d6:F00 "  111
brk   ""

# Timplate Input  Group 2

PINS RESETB 
  0   " d1:F00 d3:F10 "  0
  1   " d1:F10 d3:F10 "  1
  5   " d4:F00 d2:F10 d5:F00 d7:F10 d8:F00 d6:F10 "  000
  6   " d4:F10 d2:F10 d5:F10 d7:F10 d8:F10 d6:F10 "  111
brk   ""

# Timplate Output Group 0

PINS DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[13] DRAM0_A[12] DRAM0_A[11] DRAM0_A[10] DRAM0_A[9] DRAM0_A[8] DRAM0_A[7] DRAM0_A[6] DRAM0_A[5] DRAM0_A[4] DRAM0_A[3] DRAM0_A[2] DRAM0_A[1] DRAM0_A[0] DRAM0_BA[1] DRAM0_BA[0] DRAM0_DM[3] DRAM0_DM[2] DRAM0_DM[1] DRAM0_DM[0] DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[13] DRAM1_A[12] DRAM1_A[11] DRAM1_A[10] DRAM1_A[9] DRAM1_A[8] DRAM1_A[7] DRAM1_A[6] DRAM1_A[5] DRAM1_A[4] DRAM1_A[3] DRAM1_A[2] DRAM1_A[1] DRAM1_A[0] DRAM1_BA[1] DRAM1_BA[0] DRAM1_DM[3] DRAM1_DM[2] DRAM1_DM[1] DRAM1_DM[0] SO0_ACLK SO0_CLK SO0_LRCLK SO0_DATA1 SO0_DATA2 SO0_DATA3 SO0_DATA4 SO0_DATA5 SO0_SPDIF SO1_ACLK SO1_CLK SO1_LRCLK SO1_DATA1 SO1_DATA2 SO1_DATA3 SO1_DATA4 SO1_DATA5 SO1_SPDIF HDMI_PDB VO0_CLK VO0_P[23] VO0_P[22] VO0_P[21] VO0_P[20] VO0_P[19] VO0_P[18] VO0_P[17] VO0_P[16] VO0_P[15] VO0_P[14] VO0_P[13] VO0_P[12] VO0_P[11] VO0_P[10] VO0_P[9] VO0_P[8] VO0_P[7] VO0_P[6] VO0_P[5] VO0_P[4] VO0_P[3] VO0_P[2] VO0_P[1] VO0_P[0] VO0_VLD PCI_AD[31] PCI_AD[30] PCI_CBEB[3] PCI_CBEB[2] PCI_CBEB[1] PCI_CBEB[0] PCI_PAR PCI_FRAMEB PCI_TRDYB PCI_IRDYB PCI_STOPB PCI_DEVSELB PCI_INTAB PB_A[24] PB_A[23] PB_A[22] PB_A[21] PB_A[20] PB_A[19] PB_A[18] PB_A[17] PB_A[16] PB_CSB[3] PB_CSB[2] PB_CSB[1] PB_CSB[0] PB_RDB PB_WRB PB_ALE PB_DMACKB PB_DIRB IDE_HIORN IDE_HIOWN IDE_DACKN IDE_HA[2] IDE_HA[1] IDE_HA[0] IDE_CS0N IDE_CS1N IDE_HD[15] IDE_HD[14] IDE_HD[13] IDE_HD[12] IDE_HD[11] IDE_HD[10] IDE_HD[9] IDE_HD[8] IDE_HD[7] IDE_HD[6] IDE_HD[5] IDE_HD[4] IDE_HD[3] IDE_HD[2] IDE_HD[1] IDE_HD[0] ETH_TXCLK ETH_TX_EN ETH_TXD[3] ETH_TXD[2] ETH_TXD[1] ETH_TXD[0] ETH_RXCLK ETH_RX_DV ETH_RX_ER ETH_RXD[3] ETH_RXD[2] ETH_RXD[1] ETH_RXD[0] ETH_CRS ETH_COL ETH_MDC ETH_MDIO ETH_MDINTB ETH_GPIO[15] ETH_GPIO[14] ETH_GPIO[13] ETH_GPIO[12] ETH_GPIO[11] ETH_GPIO[10] ETH_GPIO[9] ETH_GPIO[8] ETH_GPIO[7] ETH_GPIO[6] ETH_GPIO[5] ETH_GPIO[4] ETH_GPIO[3] ETH_GPIO[2] ETH_GPIO[1] ETH_GPIO[0] UART0_RX UART0_CTS UART0_DSR UART0_DCD UART0_TX UART0_RTS UART0_DTR UART1_RX UART1_CTS UART1_DSR UART1_DCD UART1_TX UART1_RTS UART1_DTR SCARD_RST SCARD_CLK SCARD_FCB SCARD_IO SCARD_CTL[2] SCARD_CTL[1] SCARD_CTL[0] RTC_XTAL_OUT RTC_RING RTC_CLK_OUT XTAL_OUT RCLK1_XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT GPIO[13] GPIO[12] GPIO[11] GPIO[10] GPIO[9] GPIO[8] GPIO[7] GPIO[6] 
  2   " r1:X "  X
  3   " r1:L "  L
  4   " r1:H "  H
  7   " r2:X r3:X r4:X "  XXX
  8   " r2:L r3:L r4:L "  LLL
  9   " r2:H r3:H r4:H "  HHH

# Timplate InOut  Group 0

PINS DRAM0_DQ[31] DRAM0_DQ[30] DRAM0_DQ[29] DRAM0_DQ[28] DRAM0_DQ[27] DRAM0_DQ[26] DRAM0_DQ[25] DRAM0_DQ[24] DRAM0_DQ[23] DRAM0_DQ[22] DRAM0_DQ[21] DRAM0_DQ[20] DRAM0_DQ[19] DRAM0_DQ[18] DRAM0_DQ[17] DRAM0_DQ[16] DRAM0_DQ[15] DRAM0_DQ[14] DRAM0_DQ[13] DRAM0_DQ[12] DRAM0_DQ[11] DRAM0_DQ[10] DRAM0_DQ[9] DRAM0_DQ[8] DRAM0_DQ[7] DRAM0_DQ[6] DRAM0_DQ[5] DRAM0_DQ[4] DRAM0_DQ[3] DRAM0_DQ[2] DRAM0_DQ[1] DRAM0_DQ[0] DRAM1_DQ[31] DRAM1_DQ[30] DRAM1_DQ[29] DRAM1_DQ[28] DRAM1_DQ[27] DRAM1_DQ[26] DRAM1_DQ[25] DRAM1_DQ[24] DRAM1_DQ[23] DRAM1_DQ[22] DRAM1_DQ[21] DRAM1_DQ[20] DRAM1_DQ[19] DRAM1_DQ[18] DRAM1_DQ[17] DRAM1_DQ[16] DRAM1_DQ[15] DRAM1_DQ[14] DRAM1_DQ[13] DRAM1_DQ[12] DRAM1_DQ[11] DRAM1_DQ[10] DRAM1_DQ[9] DRAM1_DQ[8] DRAM1_DQ[7] DRAM1_DQ[6] DRAM1_DQ[5] DRAM1_DQ[4] DRAM1_DQ[3] DRAM1_DQ[2] DRAM1_DQ[1] DRAM1_DQ[0] HDMI_DSCL HDMI_DSDA PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_IDSEL[0] PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] 
  0   " d1:F00 r1:X "  0
  1   " d1:F10 r1:X "  1
  2   " d1:F0Z r1:X "  X
  3   " d1:F0Z r1:L "  L
  4   " d1:F0Z r1:H "  H
  5   " d3:F00 d4:F00 d2:F00 r2:X r3:X r4:X "  000
  6   " d3:F10 d4:F10 d2:F10 r2:X r3:X r4:X "  111
  7   " d1:F0Z r2:X r3:X r4:X "  XXX
  8   " d1:F0Z r2:L r3:L r4:L "  LLL
  9   " d1:F0Z r2:H r3:H r4:H "  HHH

#########################################
###   WAVETABLE FOR SCAN PINS         ###
#########################################


PINS PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] GPIO[15] GPIO[14]
  2   " r1:X "  X
  3   " r1:L "  L
  4   " r1:H "  H
  5   " r2:X r3:X r4:X "  XXX
  6   " r2:X r3:X r4:L "  XXL
  7   " r2:X r3:X r4:H "  XXH
  8   " r2:X r3:L r4:X "  XLX
  9   " r2:X r3:L r4:L "  XLL
  a   " r2:X r3:L r4:H "  XLH
  b   " r2:X r3:H r4:X "  XHX
  c   " r2:X r3:H r4:L "  XHL
  d   " r2:X r3:H r4:H "  XHH
  e   " r2:L r3:X r4:X "  LXX
  f   " r2:L r3:X r4:L "  LXL
 10   " r2:L r3:X r4:H "  LXH
 11   " r2:L r3:L r4:X "  LLX
 12   " r2:L r3:L r4:L "  LLL
 13   " r2:L r3:L r4:H "  LLH
 14   " r2:L r3:H r4:X "  LHX
 15   " r2:L r3:H r4:L "  LHL
 16   " r2:L r3:H r4:H "  LHH
 17   " r2:H r3:X r4:X "  HXX
 18   " r2:H r3:X r4:L "  HXL
 19   " r2:H r3:X r4:H "  HXH
 1a   " r2:H r3:L r4:X "  HLX
 1b   " r2:H r3:L r4:L "  HLL
 1c   " r2:H r3:L r4:H "  HLH
 1d   " r2:H r3:H r4:X "  HHX
 1e   " r2:H r3:H r4:L "  HHL
 1f   " r2:H r3:H r4:H "  HHH

PINS PB_AD[15] PB_AD[14] PB_AD[13] PB_AD[12] PB_AD[11] PB_AD[10] PB_AD[9] PB_AD[8] PB_AD[7] PB_AD[6] PB_AD[5] PB_AD[4] PB_AD[3] PB_AD[2] PB_AD[1] PB_AD[0] PB_A[15] PB_A[14] PB_A[13] PB_A[12] PB_A[11] PB_A[10] PB_A[9] PB_A[8] PB_A[7] PB_A[6] PB_A[5] PB_A[4] PB_A[3] PB_A[2] PB_A[1] PB_A[0]
  0   " d1:F00 "  0
  1   " d1:F10 "  1
  5   " d3:F00 d4:F00 d2:F00 "  000
  6   " d3:F00 d4:F00 d2:F10 "  001
  7   " d3:F00 d4:F10 d2:F00 "  010
  8   " d3:F00 d4:F10 d2:F10 "  011
  9   " d3:F10 d4:F00 d2:F00 "  100
  a   " d3:F10 d4:F00 d2:F10 "  101
  b   " d3:F10 d4:F10 d2:F00 "  110
  c   " d3:F10 d4:F10 d2:F10 "  111
brk   ""

# Version  : TgenVcd Version 8.31 Release Dec-05 2005
# Date     : 22:45:37 Thursday December 8, 2005
# File     : dump_bist_12_8.timing (93k equation timing file)
#
##########################################################
#    Timing Wave Table - bist                            #
##########################################################
WAVETBL "bist" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"

#
# Added clocks
#
PINS VI0_CLK VI1_CLK VI2_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"

PINS RCLK0_IN
#
#  Input RZ  X1 Mode 
#
  4   "d1:F00"         0
  5   "d1:F10 d2:F0N"  1
  brk "d1:F00"

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
# 051213 masked PCI_AD[0] PCI_AD[16] & PCI_PAR
#
PINS PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


######################################
#    maskout signals                 #
######################################

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

#PINS tg1O5
PINS RCLK1_XTAL_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS XTAL_BUF 
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_AD[0] PCI_AD[16] PCI_PAR 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
# Version  : TgenVcd Version 8.31 Release Dec-08 2005
# Date     : 20:52:21 Monday December 12, 2005
# File     : dump_serial_flash_12_10.timing (93k equation timing file)
#
##########################################################
#    Timing Wave Table - serial flash                    #
##########################################################

WAVETBL "serial_flash" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


#PINS tg1I0
PINS XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1I2
PINS PCI_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"         

PINS RCLK0_IN
  4   " d1:F00 "  0
  5   " d1:F10 d2:F00"  1
brk   " d1:F00 "  

#PINS tg1B3
# 
# mask PCI_AD[0] PCI_AD[16] PCI_PAR PCI_TRDYB PCI_DEVSELB
# 
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B5
PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B6
PINS PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B7
PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#######################################
####   mask pins                   ####
#######################################
PINS PCI_AD[0] PCI_AD[16] PCI_PAR PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
##########################################################
#    Timing Wave Table - dac                             #
##########################################################
WAVETBL "dac" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"  

#
# Added clocks
#
PINS VI0_CLK VI1_CLK VI2_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"  

PINS RCLK0_IN
#
#  Input RZ  X1 Mode 
#
  4   "d1:F00"         0
  5   "d1:F10 d2:F0N"  1
  brk "d1:F00"

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
# 051213 masked PCI_AD[0] & PCI_PAR
#
PINS PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


######################################
#    maskout signals                 #
######################################

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

#PINS tg1O5
PINS RCLK1_XTAL_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS XTAL_BUF 
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_AD[0] PCI_PAR 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


#
##########################################################
#    PLL  Timing Wave Table 03/18/06                     #
#         Same as dac except RCLK3_OUT is ON             #
#         - RZ and RO clocks will have pulsed break cyc  #
#         - use dac setup1 for skip sf check             #
##########################################################
WAVETBL "pll" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F00 d2:F1N"  

#
# Added clocks
#
PINS VI0_CLK VI1_CLK VI2_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F00 d2:F1N"  

PINS RCLK0_IN
#
#  Input RZ  X1 Mode 
#
  4   "d1:F00"         0
  5   "d1:F10 d2:F0N"  1
  brk "d1:F10 d2:F0N"  

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
# 051213 masked PCI_AD[0] & PCI_PAR
#
PINS PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


PINS RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

######################################
#    maskout signals                 #
######################################
PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT 
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

#PINS tg1O5
PINS RCLK1_XTAL_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS XTAL_BUF 
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_AD[0] PCI_PAR 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
##########################################################
#    Timing Wave Table - serial flash                    #
##########################################################
WAVETBL "serial_flash_bist" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


#PINS tg1I0
#
#add XTAL_IN 060217
#
PINS XTAL_IN XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1I2
PINS PCI_CLK RCLK1_XTAL_IN  VI0_CLK  VI1_CLK  VI2_CLK  VCXO0_IN  VCXO1_IN  
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"         

PINS RCLK0_IN
  4   " d1:F00 "  0
  5   " d1:F10 d2:F00"  1
brk   " d1:F00 "  


#PINS tg1B3
# 
# mask PCI_AD[0] PCI_PAR PCI_TRDYB PCI_DEVSELB
# 
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B5
PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B6
PINS GPIO[13] PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B7
PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


######################################
#    maskout signals                 #
######################################
PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

#PINS tg1O5
PINS RCLK1_XTAL_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS XTAL_BUF 
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_AD[0] PCI_PAR 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#######################################
####   mask pins                   ####
#######################################
PINS PCI_AD[0] PCI_PAR PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


#
##########################################################
#    WAVE TABLE serialization                            #
##########################################################
# 08/21/06 Change timing style for VDCP editint

WAVETBL "serialization" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 
WFDF 0  D11  .   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

PINS USB20_XI
WFDF 0  D11  .   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

PINS USB20_XO
WFDF 0  .   .   .  EE1  .   .
6   .   .   X   .
7   .   .   L   .
8   .   .   H   .
9   .   .   X   .
DCDF ts0    0

PINS WDA_SYNC
WFDF 0  D11  .   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF     .   .   .   .   .   .
DCDF ts0    0


PINS XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
#
#  Input NRZ X1 Mode 
#
WFDF 0  D11  .   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
WFDF 0  D11  .   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

PINS PCI_CLK
#
#  Input RO  X1 Mode 
#
WFDF 0  D11 F1N   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF    F10 F1N   .   .   .   .
DCDF ts0    0


PINS RCLK0_IN
WFDF 0  D11 F00   .   .   .   .
4   0   .   .   .
5   1   .   .   .
BWDF    F00 F00   .   .   .   .
DCDF ts0    0


# 
# mask PCI_AD[0] PCI_AD[16] PCI_PAR PCI_TRDYB PCI_DEVSELB
# 
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
WFDF 0  D11  .   .  EE1  .   .
4   0   .   X   .
5   1   .   X   .
6 F0Z   .   X   .
7 F0Z   .   L   .
8 F0Z   .   H   .
9 F0Z   .   X   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
WFDF 0  D11  .   .  EE1  .   .
4   0   .   X   .
5   1   .   X   .
6 F0Z   .   X   .
7 F0Z   .   L   .
8 F0Z   .   H   .
9 F0Z   .   X   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
WFDF 0  D11  .   .  EE1  .   .
4   0   .   X   .
5   1   .   X   .
6 F0Z   .   X   .
7 F0Z   .   L   .
8 F0Z   .   H   .
9 F0Z   .   X   .
BWDF     .   .   .   .   .   .
DCDF ts0    0


PINS PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
WFDF 0  D11  .   .  EE1  .   .
4   0   .   X   .
5   1   .   X   .
6 F0Z   .   X   .
7 F0Z   .   L   .
8 F0Z   .   H   .
9 F0Z   .   X   .
BWDF     .   .   .   .   .   .
DCDF ts0    0


#PINS tg1B7
PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
WFDF 0  D11  .   .  EE1  .   .
4   0   .   X   .
5   1   .   X   .
6 F0Z   .   X   .
7 F0Z   .   L   .
8 F0Z   .   H   .
9 F0Z   .   X   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

#######################################
####   mask pins                   ####
#######################################
PINS PCI_AD[0] PCI_AD[16] PCI_PAR PCI_TRDYB PCI_DEVSELB
WFDF 0  D11  .   .  EE1  .   .
4   0   .   X   .
5   1   .   X   .
6 F0Z   .   X   .
7 F0Z   .   X   .
8 F0Z   .   X   .
9 F0Z   .   X   .
BWDF     .   .   .   .   .   .
DCDF ts0    0

#
##########################################################
#    dram bist   Wave Table                              #
##########################################################
WAVETBL "dram_bist" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"

#
# Added clocks
#
PINS VI0_CLK VI1_CLK VI2_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"

PINS RCLK0_IN
#
#  Input RZ  X1 Mode 
#
  4   "d1:F00"         0
  5   "d1:F10 d2:F0N"  1
  brk "d1:F00"

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
# 051213 masked PCI_AD[0] PCI_AD[16] & PCI_PAR
#
PINS PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


#################################################
###   09/23/2006   DRAM0, DRAM1               ###
#################################################
PINS DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[0] DRAM0_A[1] DRAM0_A[2] DRAM0_A[3] DRAM0_A[4] DRAM0_A[5] DRAM0_A[6] DRAM0_A[7] DRAM0_A[8] DRAM0_A[9] DRAM0_A[10] DRAM0_A[11] DRAM0_A[12] DRAM0_A[13] DRAM0_BA[0] DRAM0_BA[1] DRAM0_DM[0] DRAM0_DM[1] DRAM0_DM[2] DRAM0_DM[3] 
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:L"  L
  8   "r1:H"  H
  9   "r1:X"  Z

PINS DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[0] DRAM1_A[1] DRAM1_A[2] DRAM1_A[3] DRAM1_A[4] DRAM1_A[5] DRAM1_A[6] DRAM1_A[7] DRAM1_A[8] DRAM1_A[9] DRAM1_A[10] DRAM1_A[11] DRAM1_A[12] DRAM1_A[13] DRAM1_BA[0] DRAM1_BA[1] DRAM1_DM[0] DRAM1_DM[1] DRAM1_DM[2] DRAM1_DM[3]
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:L"  L
  8   "r1:H"  H
  9   "r1:X"  Z

PINS DRAM0_DQS[0] DRAM0_DQS[1] DRAM0_DQS[2] DRAM0_DQS[3] DRAM0_DQ[0] DRAM0_DQ[1] DRAM0_DQ[2] DRAM0_DQ[3] DRAM0_DQ[4] DRAM0_DQ[5] DRAM0_DQ[6] DRAM0_DQ[7] DRAM0_DQ[8] DRAM0_DQ[9] DRAM0_DQ[10] DRAM0_DQ[11] DRAM0_DQ[12] DRAM0_DQ[13] DRAM0_DQ[14] DRAM0_DQ[15] DRAM0_DQ[16] DRAM0_DQ[17] DRAM0_DQ[18] DRAM0_DQ[19] DRAM0_DQ[20] DRAM0_DQ[21] DRAM0_DQ[22] DRAM0_DQ[23] DRAM0_DQ[24] DRAM0_DQ[25] DRAM0_DQ[26] DRAM0_DQ[27] DRAM0_DQ[28] DRAM0_DQ[29] DRAM0_DQ[30] DRAM0_DQ[31] 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS DRAM1_DQS[0] DRAM1_DQS[1] DRAM1_DQS[2] DRAM1_DQS[3] DRAM1_DQ[0] DRAM1_DQ[1] DRAM1_DQ[2] DRAM1_DQ[3] DRAM1_DQ[4] DRAM1_DQ[5] DRAM1_DQ[6] DRAM1_DQ[7] DRAM1_DQ[8] DRAM1_DQ[9] DRAM1_DQ[10] DRAM1_DQ[11] DRAM1_DQ[12] DRAM1_DQ[13] DRAM1_DQ[14] DRAM1_DQ[15] DRAM1_DQ[16] DRAM1_DQ[17] DRAM1_DQ[18] DRAM1_DQ[19] DRAM1_DQ[20] DRAM1_DQ[21] DRAM1_DQ[22] DRAM1_DQ[23] DRAM1_DQ[24] DRAM1_DQ[25] DRAM1_DQ[26] DRAM1_DQ[27] DRAM1_DQ[28] DRAM1_DQ[29] DRAM1_DQ[30] DRAM1_DQ[31]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

######################################
#    maskout signals                 #
######################################

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

#PINS tg1O5
PINS RCLK1_XTAL_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS XTAL_BUF 
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_TRDYB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

PINS PCI_AD[0] PCI_AD[16] PCI_PAR 
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

##########################################################
#    12/06/06 atspeed bist_5us                           #
#    - RCLK1_XTAL_IN on for 5us first                    #
#    - RCLK0_IN 1 = NRZ 1.                               #
#               0 = RZ                                   #
##########################################################
WAVETBL "atspeed_bist_5us" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################
PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#PINS tg1I0
PINS XTAL_IN XTAL_DISC VCXO0_IN VCXO1_IN RCLK1_XTAL_IN TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3] PCI_CLK
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

###########################################
##  added VIx_CLK (need to run 2x freq)  ##
###########################################
PINS VI0_CLK VI1_CLK VI2_CLK
  4   " d1:F00 d2:F10 d3:F00 d4:F10"  0
  5   " d1:F10 "                      1
  brk " d1:F10"

#PINS tg1I1
PINS RCLK0_IN
#
#  Input RZ  X1 Mode 
#
# 4   "d1:F00"         0
# 5   "d1:F10 d2:F0N"  1
# brk "d1:F00"
  4   "d1:F10 d2:F00"  0
  5   "d1:F10"         1
  brk "d1:F00"

#PINS tg1I2
PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1O3
PINS XTAL_OUT 
  6   "r1:X"  X
  7   "r1:L"  L
  8   "r1:H"  H
  9   "r1:X"  Z


#PINS tg1B5
PINS XTAL_BUF PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B6
PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] 

#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B7
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[2] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B8
PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


###########################################
##  added GPIO signals                   ##
###########################################
PINS GPIO[0]
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15]
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

######################################
#    maskout signals                 #
######################################
#PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
PINS RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS XTAL_OUT RCLK1_XTAL_OUT
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z

PINS PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:X"  L
  8   "d3:F0Z r1:X"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""


##########################################################
#    Wave Table for display_func (Horizontal Noise)      #
##########################################################
# Version  : TgenVcd Version 8.33 Release Nov-24 2006
# Date     : 20:55:23 Thursday January 25, 2007
# File     : display_func_M804o_0125_d.timing (93k equation timing file)
#
WAVETBL "display_func" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################
PINS VO0_VLD
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z
  a   " r2:H r3:H r4:H"  h
  b   " r2:H r3:H r4:L"  i
  c   " r2:H r3:L r4:L"  j
  d   " r2:L r3:L r4:L"  l
  e   " r2:L r3:L r4:H"  m
  f   " r2:L r3:H r4:H"  n

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""


PINS USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS VI0_CLK VI1_CLK VI2_CLK
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS XTAL_IN XTAL_DISC VCXO0_IN VCXO1_IN TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

####################################
### 3/15/07 add RCLK1_XTAL_IN    ###
###         to match RCLK0_IN    ###
####################################
PINS RCLK1_XTAL_IN
  4   "d1:F10 d2:F0N"  0
  5   "d1:F10 d2:F0N"  1
# brk "d1:F10 d2:F0N"  
  brk "d2:F0N"   

PINS RCLK0_IN 
#
#  Input RZ  X1 Mode 
#
  4   "d1:F00"         0
  5   "d1:F10 d2:F0N"  1
# brk "d1:F10 d2:F0N"  
  brk "d2:F0N"   

#PINS tg1I2
PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1O3
PINS XTAL_OUT RCLK1_XTAL_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:L"  L
  8   "r1:H"  H
  9   "r1:X"  Z

#PINS tg1O4
PINS RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:L"  L
  8   "r1:H"  H
  9   "r1:X"  Z

#PINS tg1B5
PINS XTAL_BUF PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B6
PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B7
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_IRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B8
PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B9
PINS PCI_PAR PCI_STOPB PCI_DEVSELB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B10
PINS PCI_FRAMEB
#
#  IO RO  + Edge Strobe X1 Mode 
#
  4   "d1:F00 d2:F1N r1:X"  0
  5   "d1:F10        r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B11
PINS PCI_TRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B12
PINS PCI_IDSEL[0]
#
#  IO RZ  + Edge Strobe X1 Mode 
#
  4   "d1:F00        r1:X"  0
  5   "d1:F10 d2:F0N r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#
# Version  : TgenVcd Version 8.33 Release Nov-24 2006
# Date     : 08:59:42 Saturday February 17, 2007
# File     : dram_func_M804q_070215_p.timing (93k equation timing file)
#
##########################################################
#    Timing Wave Table  (dram_func_M804q_070215_p)       #
##########################################################
WAVETBL "dram_func" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XI
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

PINS USB20_XO
  6   " r1:X "  X
  7   " r1:L "  L
  8   " r1:H "  H
  9   " r1:X "  Z

PINS WDA_SYNC
  4   " d1:F00 "  0
  5   " d1:F10 "  1
brk   ""

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VI0_CLK VI1_CLK VI2_CLK
#
#  Input RO  X1 Mode 
#
  4   "d1:F00 d2:F1N"  0
  5   "d1:F10"         1
  brk "d1:F10"

PINS tg1I0
PINS XTAL_IN XTAL_DISC VCXO0_IN VCXO1_IN RCLK1_XTAL_IN TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1I1
PINS RCLK0_IN
#
#  Input RZ  X1 Mode 
#
  4   "d1:F00"         0
  5   "d1:F10 d2:F0N"  1
  brk ""

#PINS tg1I2
PINS RESETB PCI_REQB[0]
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1I3
PINS PCI_CLK
#
#  Input NRZ X1 Mode 
#
  4   "d1:F00"  0
  5   "d1:F10"  1

#PINS tg1O4
PINS XTAL_OUT RCLK1_XTAL_OUT DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[0] DRAM0_A[1] DRAM0_A[2] DRAM0_A[3] DRAM0_A[4] DRAM0_A[5] DRAM0_A[6] DRAM0_A[7] DRAM0_A[8] DRAM0_A[9] DRAM0_A[10] DRAM0_A[11] DRAM0_A[12] DRAM0_A[13] DRAM0_BA[0] DRAM0_BA[1] DRAM0_DM[0] DRAM0_DM[1] DRAM0_DM[2] DRAM0_DM[3] DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[0] DRAM1_A[1] DRAM1_A[2] DRAM1_A[3] DRAM1_A[4] DRAM1_A[5] DRAM1_A[6] DRAM1_A[7] DRAM1_A[8] DRAM1_A[9] DRAM1_A[10] DRAM1_A[11] DRAM1_A[12] DRAM1_A[13] DRAM1_BA[0] DRAM1_BA[1] DRAM1_DM[0] DRAM1_DM[1] DRAM1_DM[2] DRAM1_DM[3]
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:L"  L
  8   "r1:H"  H
  9   "r1:X"  Z

#PINS tg1B6
PINS XTAL_BUF PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB DRAM0_DQS[0] DRAM0_DQS[1] DRAM0_DQS[2] DRAM0_DQS[3] DRAM0_DQ[0] DRAM0_DQ[1] DRAM0_DQ[2] DRAM0_DQ[3] DRAM0_DQ[4] DRAM0_DQ[5] DRAM0_DQ[6] DRAM0_DQ[7] DRAM0_DQ[8] DRAM0_DQ[9] DRAM0_DQ[10] DRAM0_DQ[11] DRAM0_DQ[12] DRAM0_DQ[13] DRAM0_DQ[14] DRAM0_DQ[15] DRAM0_DQ[16] DRAM0_DQ[17] DRAM0_DQ[18] DRAM0_DQ[19] DRAM0_DQ[20] DRAM0_DQ[21] DRAM0_DQ[22] DRAM0_DQ[23] DRAM0_DQ[24] DRAM0_DQ[25] DRAM0_DQ[26] DRAM0_DQ[27] DRAM0_DQ[28] DRAM0_DQ[29] DRAM0_DQ[30] DRAM0_DQ[31] DRAM1_DQS[0] DRAM1_DQS[1] DRAM1_DQS[2] DRAM1_DQS[3] DRAM1_DQ[0] DRAM1_DQ[1] DRAM1_DQ[2] DRAM1_DQ[3] DRAM1_DQ[4] DRAM1_DQ[5] DRAM1_DQ[6] DRAM1_DQ[7] DRAM1_DQ[8] DRAM1_DQ[9] DRAM1_DQ[10] DRAM1_DQ[11] DRAM1_DQ[12] DRAM1_DQ[13] DRAM1_DQ[14] DRAM1_DQ[15] DRAM1_DQ[16] DRAM1_DQ[17] DRAM1_DQ[18] DRAM1_DQ[19] DRAM1_DQ[20] DRAM1_DQ[21] DRAM1_DQ[22] DRAM1_DQ[23] DRAM1_DQ[24] DRAM1_DQ[25] DRAM1_DQ[26] DRAM1_DQ[27] DRAM1_DQ[28] DRAM1_DQ[29] DRAM1_DQ[30] DRAM1_DQ[31]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B7
PINS PCI_AD[0] PCI_AD[2] PCI_AD[8] PCI_AD[12] PCI_AD[18] PCI_AD[20] PCI_AD[21] PCI_AD[25] PCI_AD[26] PCI_AD[31] PCI_STOPB PCI_DEVSELB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B8
PINS PCI_AD[1] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[19] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_PAR PCI_TRDYB
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B9
PINS PCI_CBEB[0] PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

#PINS tg1B10
PINS PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X1 Mode 
#
  4   "d1:F00 r1:X"  0
  5   "d1:F10 r1:X"  1
  6   "d3:F0Z r1:X"  X
  7   "d3:F0Z r1:L"  L
  8   "d3:F0Z r1:H"  H
  9   "d3:F0Z r1:X"  Z
  brk  ""

##############################
###  masked out signals    ###
##############################
PINS RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
#
#  Output Edge Strobe X1 Mode 
#
  6   "r1:X"  X
  7   "r1:X"  L
  8   "r1:X"  H
  9   "r1:X"  Z


#
# Version  : TgenVcd Version 8.33 Release Nov-24 2006
# Date     : 20:42:25 Sunday December 31, 2006
# File     : serialization_M450_12_04_dev.timing (93k x2 equation timing file)
#
##########################################################
#    Timing Wave Table                                   #
##########################################################

WAVETBL "serial_flash_x2" # wave table definition

#DISPLAY multi

#########################################
###   WAVETABLE FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS DRAM0_VREFSSTL1
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS DRAM0_VREFSSTL23
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS DRAM1_VREFSSTL0
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS DRAM1_VREFSSTL1
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS DRAM1_VREFSSTL23
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS USB20_XI
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS USB20_XO
#
#  Output Edge Strobe X2 Mode 
#
  4   " r1:X r2:X "  XX
  5   " r1:X r2:L "  XL
  6   " r1:X r2:H "  XH
  7   " r1:L r2:X "  LX
  8   " r1:L r2:L "  LL
  9   " r1:L r2:H "  LH
  a   " r1:H r2:X "  HX
  b   " r1:H r2:L "  HL
  c   " r1:H r2:H "  HH

PINS WDA_SYNC
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

PINS RCLK0_IN
#
#  input NRZ (Non Return to zero) X2 Mode
#
# 0   " d1:F00 d4:F00 "  00
# 1   " d1:F00 d4:F10 "  01
# 2   " d1:F10 d4:F00 "  10
# 3   " d1:F10 d4:F10 "  11
  0   " d1:F00 d2:F00 d4:F00 d5:F00 "  00
  1   " d1:F00 d2:F00 d4:F10 d5:F00 "  01
  2   " d1:F10 d2:F00 d4:F00 d5:F00 "  10
  3   " d1:F10 d2:F00 d4:F10 d5:F00 "  11
  brk ""

#PINS tg1I0
PINS XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#
#  input NRZ (Non Return to zero) X2 Mode
#
  0   " d1:F00 d4:F00 "  00
  1   " d1:F00 d4:F10 "  01
  2   " d1:F10 d4:F00 "  10
  3   " d1:F10 d4:F10 "  11
  brk ""

#PINS tg1I2
PINS PCI_CLK
#
#  input RO (Return to One)  X2 Mode
#
  0   " d1:F00 d2:F10 d4:F00 d5:F10 "  00
  1   " d1:F00 d2:F10 d4:F10 d5:F10 "  01
  2   " d1:F10 d2:F10 d4:F00 d5:F10 "  10
  3   " d1:F10 d2:F10 d4:F10 d5:F10 "  11
  brk ""

#PINS tg1B3
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_STOPB 
#
#  IO NRZ + Edge Strobe X2 Mode 
#
  0   " d1:F00 d4:F00 r1:X r2:X "  00
  1   " d1:F00 d4:F10 r1:X r2:X "  01
  2   " d1:F10 d4:F00 r1:X r2:X "  10
  3   " d1:F10 d4:F10 r1:X r2:X "  11
  4   " d3:F0Z d6:F0Z r1:X r2:X "  XX
  5   " d3:F0Z d6:F0Z r1:X r2:L "  XL
  6   " d3:F0Z d6:F0Z r1:X r2:H "  XH
  7   " d3:F0Z d6:F0Z r1:L r2:X "  LX
  8   " d3:F0Z d6:F0Z r1:L r2:L "  LL
  9   " d3:F0Z d6:F0Z r1:L r2:H "  LH
  a   " d3:F0Z d6:F0Z r1:H r2:X "  HX
  b   " d3:F0Z d6:F0Z r1:H r2:L "  HL
  c   " d3:F0Z d6:F0Z r1:H r2:H "  HH
 10   " d1:F00 d6:F0Z r1:X r2:X "  0X
 11   " d1:F00 d6:F0Z r1:X r2:L "  0L
 12   " d1:F00 d6:F0Z r1:X r2:H "  0H
 13   " d1:F10 d6:F0Z r1:X r2:X "  1X
 14   " d1:F10 d6:F0Z r1:X r2:L "  1L
 15   " d1:F10 d6:F0Z r1:X r2:H "  1H
 16   " d3:F0Z d4:F00 r1:X r2:X "  X0
 17   " d3:F0Z d4:F10 r1:X r2:X "  X1
 18   " d3:F0Z d4:F00 r1:L r2:X "  L0
 19   " d3:F0Z d4:F10 r1:L r2:X "  L1
 1a   " d3:F0Z d4:F00 r1:H r2:X "  H0
 1b   " d3:F0Z d4:F10 r1:H r2:X "  H1
  brk ""


#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
#
#  IO NRZ + Edge Strobe X2 Mode 
#
  0   " d1:F00 d4:F00 r1:X r2:X "  00
  1   " d1:F00 d4:F10 r1:X r2:X "  01
  2   " d1:F10 d4:F00 r1:X r2:X "  10
  3   " d1:F10 d4:F10 r1:X r2:X "  11
  4   " d3:F0Z d6:F0Z r1:X r2:X "  XX
  5   " d3:F0Z d6:F0Z r1:X r2:L "  XL
  6   " d3:F0Z d6:F0Z r1:X r2:H "  XH
  7   " d3:F0Z d6:F0Z r1:L r2:X "  LX
  8   " d3:F0Z d6:F0Z r1:L r2:L "  LL
  9   " d3:F0Z d6:F0Z r1:L r2:H "  LH
  a   " d3:F0Z d6:F0Z r1:H r2:X "  HX
  b   " d3:F0Z d6:F0Z r1:H r2:L "  HL
  c   " d3:F0Z d6:F0Z r1:H r2:H "  HH
 10   " d1:F00 d6:F0Z r1:X r2:X "  0X
 11   " d1:F00 d6:F0Z r1:X r2:L "  0L
 12   " d1:F00 d6:F0Z r1:X r2:H "  0H
 13   " d1:F10 d6:F0Z r1:X r2:X "  1X
 14   " d1:F10 d6:F0Z r1:X r2:L "  1L
 15   " d1:F10 d6:F0Z r1:X r2:H "  1H
 16   " d3:F0Z d4:F00 r1:X r2:X "  X0
 17   " d3:F0Z d4:F10 r1:X r2:X "  X1
 18   " d3:F0Z d4:F00 r1:L r2:X "  L0
 19   " d3:F0Z d4:F10 r1:L r2:X "  L1
 1a   " d3:F0Z d4:F00 r1:H r2:X "  H0
 1b   " d3:F0Z d4:F10 r1:H r2:X "  H1
  brk ""

#PINS tg1B5
PINS PCI_CBEB[2]
#
#  IO NRZ + Edge Strobe X2 Mode 
#
  0   " d1:F00 d4:F00 r1:X r2:X "  00
  1   " d1:F00 d4:F10 r1:X r2:X "  01
  2   " d1:F10 d4:F00 r1:X r2:X "  10
  3   " d1:F10 d4:F10 r1:X r2:X "  11
  4   " d3:F0Z d6:F0Z r1:X r2:X "  XX
  5   " d3:F0Z d6:F0Z r1:X r2:L "  XL
  6   " d3:F0Z d6:F0Z r1:X r2:H "  XH
  7   " d3:F0Z d6:F0Z r1:L r2:X "  LX
  8   " d3:F0Z d6:F0Z r1:L r2:L "  LL
  9   " d3:F0Z d6:F0Z r1:L r2:H "  LH
  a   " d3:F0Z d6:F0Z r1:H r2:X "  HX
  b   " d3:F0Z d6:F0Z r1:H r2:L "  HL
  c   " d3:F0Z d6:F0Z r1:H r2:H "  HH
 10   " d1:F00 d6:F0Z r1:X r2:X "  0X
 11   " d1:F00 d6:F0Z r1:X r2:L "  0L
 12   " d1:F00 d6:F0Z r1:X r2:H "  0H
 13   " d1:F10 d6:F0Z r1:X r2:X "  1X
 14   " d1:F10 d6:F0Z r1:X r2:L "  1L
 15   " d1:F10 d6:F0Z r1:X r2:H "  1H
 16   " d3:F0Z d4:F00 r1:X r2:X "  X0
 17   " d3:F0Z d4:F10 r1:X r2:X "  X1
 18   " d3:F0Z d4:F00 r1:L r2:X "  L0
 19   " d3:F0Z d4:F10 r1:L r2:X "  L1
 1a   " d3:F0Z d4:F00 r1:H r2:X "  H0
 1b   " d3:F0Z d4:F10 r1:H r2:X "  H1
  brk ""

#PINS tg1B6
PINS PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
#
#  IO NRZ + Edge Strobe X2 Mode 
#
  0   " d1:F00 d4:F00 r1:X r2:X "  00
  1   " d1:F00 d4:F10 r1:X r2:X "  01
  2   " d1:F10 d4:F00 r1:X r2:X "  10
  3   " d1:F10 d4:F10 r1:X r2:X "  11
  4   " d3:F0Z d6:F0Z r1:X r2:X "  XX
  5   " d3:F0Z d6:F0Z r1:X r2:L "  XL
  6   " d3:F0Z d6:F0Z r1:X r2:H "  XH
  7   " d3:F0Z d6:F0Z r1:L r2:X "  LX
  8   " d3:F0Z d6:F0Z r1:L r2:L "  LL
  9   " d3:F0Z d6:F0Z r1:L r2:H "  LH
  a   " d3:F0Z d6:F0Z r1:H r2:X "  HX
  b   " d3:F0Z d6:F0Z r1:H r2:L "  HL
  c   " d3:F0Z d6:F0Z r1:H r2:H "  HH
 10   " d1:F00 d6:F0Z r1:X r2:X "  0X
 11   " d1:F00 d6:F0Z r1:X r2:L "  0L
 12   " d1:F00 d6:F0Z r1:X r2:H "  0H
 13   " d1:F10 d6:F0Z r1:X r2:X "  1X
 14   " d1:F10 d6:F0Z r1:X r2:L "  1L
 15   " d1:F10 d6:F0Z r1:X r2:H "  1H
 16   " d3:F0Z d4:F00 r1:X r2:X "  X0
 17   " d3:F0Z d4:F10 r1:X r2:X "  X1
 18   " d3:F0Z d4:F00 r1:L r2:X "  L0
 19   " d3:F0Z d4:F10 r1:L r2:X "  L1
 1a   " d3:F0Z d4:F00 r1:H r2:X "  H0
 1b   " d3:F0Z d4:F10 r1:H r2:X "  H1
  brk ""

#PINS tg1B7
PINS PCI_IDSEL[0]
#
#  IO NRZ + Edge Strobe X2 Mode 
#
  0   " d1:F00 d4:F00 r1:X r2:X "  00
  1   " d1:F00 d4:F10 r1:X r2:X "  01
  2   " d1:F10 d4:F00 r1:X r2:X "  10
  3   " d1:F10 d4:F10 r1:X r2:X "  11
  4   " d3:F0Z d6:F0Z r1:X r2:X "  XX
  5   " d3:F0Z d6:F0Z r1:X r2:L "  XL
  6   " d3:F0Z d6:F0Z r1:X r2:H "  XH
  7   " d3:F0Z d6:F0Z r1:L r2:X "  LX
  8   " d3:F0Z d6:F0Z r1:L r2:L "  LL
  9   " d3:F0Z d6:F0Z r1:L r2:H "  LH
  a   " d3:F0Z d6:F0Z r1:H r2:X "  HX
  b   " d3:F0Z d6:F0Z r1:H r2:L "  HL
  c   " d3:F0Z d6:F0Z r1:H r2:H "  HH
 10   " d1:F00 d6:F0Z r1:X r2:X "  0X
 11   " d1:F00 d6:F0Z r1:X r2:L "  0L
 12   " d1:F00 d6:F0Z r1:X r2:H "  0H
 13   " d1:F10 d6:F0Z r1:X r2:X "  1X
 14   " d1:F10 d6:F0Z r1:X r2:L "  1L
 15   " d1:F10 d6:F0Z r1:X r2:H "  1H
 16   " d3:F0Z d4:F00 r1:X r2:X "  X0
 17   " d3:F0Z d4:F10 r1:X r2:X "  X1
 18   " d3:F0Z d4:F00 r1:L r2:X "  L0
 19   " d3:F0Z d4:F10 r1:L r2:X "  L1
 1a   " d3:F0Z d4:F00 r1:H r2:X "  H0
 1b   " d3:F0Z d4:F10 r1:H r2:X "  H1
  brk ""

##########################################
####    mask signals                  ####
##########################################
PINS PCI_AD[0] PCI_AD[16] PCI_PAR PCI_TRDYB PCI_DEVSELB
#
#  IO NRZ + Edge Strobe X2 Mode 
#
  0   " d1:F00 d4:F00 r1:X r2:X "  00
  1   " d1:F00 d4:F10 r1:X r2:X "  01
  2   " d1:F10 d4:F00 r1:X r2:X "  10
  3   " d1:F10 d4:F10 r1:X r2:X "  11
  4   " d3:F0Z d6:F0Z r1:X r2:X "  XX
  5   " d3:F0Z d6:F0Z r1:X r2:X "  XL
  6   " d3:F0Z d6:F0Z r1:X r2:X "  XH
  7   " d3:F0Z d6:F0Z r1:X r2:X "  LX
  8   " d3:F0Z d6:F0Z r1:X r2:X "  LL
  9   " d3:F0Z d6:F0Z r1:X r2:X "  LH
  a   " d3:F0Z d6:F0Z r1:X r2:X "  HX
  b   " d3:F0Z d6:F0Z r1:X r2:X "  HL
  c   " d3:F0Z d6:F0Z r1:X r2:X "  HH
 10   " d1:F00 d6:F0Z r1:X r2:X "  0X
 11   " d1:F00 d6:F0Z r1:X r2:X "  0L
 12   " d1:F00 d6:F0Z r1:X r2:X "  0H
 13   " d1:F10 d6:F0Z r1:X r2:X "  1X
 14   " d1:F10 d6:F0Z r1:X r2:X "  1L
 15   " d1:F10 d6:F0Z r1:X r2:X "  1H
 16   " d3:F0Z d4:F00 r1:X r2:X "  X0
 17   " d3:F0Z d4:F10 r1:X r2:X "  X1
 18   " d3:F0Z d4:F00 r1:X r2:X "  L0
 19   " d3:F0Z d4:F10 r1:X r2:X "  L1
 1a   " d3:F0Z d4:F00 r1:X r2:X "  H0
 1b   " d3:F0Z d4:F10 r1:X r2:X "  H1
  brk ""

@
EQSP TIM,EQN,#9000059435
##########################################################
#    Equation Set scan                                   #
##########################################################
EQNSET 1 "scan"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "scan"

period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#####################################
###  Equations for NON-SCAN PINS  ###
#####################################


# Timeplate Input  Group 0

PINS DRAM0_DQS[3] DRAM0_DQS[2] DRAM0_DQS[1] DRAM0_DQS[0] DRAM1_DQS[3] DRAM1_DQS[2] DRAM1_DQS[1] DRAM1_DQS[0] TS0_IN_CLK TS0_IN_VLD TS0_IN_SYNC TS0_IN_D[7] TS0_IN_D[6] TS0_IN_D[4] TS0_IN_D[3] TS0_IN_D[2] TS0_IN_D[0] TS1_IN_CLK TS1_IN_VLD TS1_IN_SYNC TS1_IN_D[7] TS1_IN_D[6] TS1_IN_D[5] TS1_IN_D[4] TS1_IN_D[3] TS1_IN_D[2] TS1_IN_D[0] TDMX_GPIO[1] TDMX_GPIO[0] SI0_SPDIF SI0_DATA SI0_CLK SI0_LRCLK SI1_SPDIF SI1_DATA SI1_CLK SI1_LRCLK HDMI_MSEN HDMI_HPD VI0_CLK VI0_P[31] VI0_P[30] VI0_P[29] VI0_P[28] VI0_P[27] VI0_P[26] VI0_P[25] VI0_P[24] VI0_P[23] VI0_P[22] VI0_P[21] VI0_P[20] VI0_P[19] VI0_P[18] VI0_P[17] VI0_P[16] VI0_P[15] VI0_P[14] VI0_P[13] VI0_P[12] VI0_P[11] VI0_P[10] VI0_P[9] VI0_P[8] VI0_P[7] VI0_P[6] VI0_P[5] VI0_P[4] VI0_P[3] VI0_P[2] VI0_P[1] VI0_P[0] VI0_VLD VI0_HS VI0_VS VI1_CLK VI1_P[7] VI1_P[6] VI1_P[5] VI1_P[4] VI1_P[3] VI1_P[2] VI1_P[1] VI1_P[0] VI1_VLD VI1_HS VI1_VS VI2_CLK VI2_VLD VI2_HS VI2_VS VO0_HS VO0_VS PCI_REQB[3] PCI_REQB[2] PCI_REQB[1] PCI_REQB[0] PB_IORDY PB_DMARQ IDE_IORDY IDE_INTRQ IDE_DMARQ IDE_NPCBLID JTAG_UART RTC_XTAL_IN RTC_TEST RTC_XTAL_DISC RTC_CLK_IN XTAL_IN XTAL_BUF XTAL_DISC RCLK1_XTAL_IN TEST 
d1 = 0.05 * Tcyc		#      5.00 ns

# Timeplate Input  Group 1

PINS TS0_IN_D[5] TS0_IN_D[1] TS1_IN_D[1] PCI_CLK VCXO0_IN VCXO1_IN RCLK0_IN GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] 
#d1 = 0.45 * Tcyc		#     45.00 ns
#d3 = 0.55 * Tcyc		#     55.00 ns
d1 = 0.35 * Tcyc		#     45.00 ns
d3 = 0.85 * Tcyc		#     55.00 ns

# Timeplate Input  Group 2

PINS RESETB 
#d1 = 0.45 * Tcyc		#     45.00 ns
#d3 = 0.55 * Tcyc		#     55.00 ns
d1 = 0.35 * Tcyc		#     45.00 ns
d3 = 0.85 * Tcyc		#     55.00 ns

# Timeplate Output Group 0

PINS DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[13] DRAM0_A[12] DRAM0_A[11] DRAM0_A[10] DRAM0_A[9] DRAM0_A[8] DRAM0_A[7] DRAM0_A[6] DRAM0_A[5] DRAM0_A[4] DRAM0_A[3] DRAM0_A[2] DRAM0_A[1] DRAM0_A[0] DRAM0_BA[1] DRAM0_BA[0] DRAM0_DM[3] DRAM0_DM[2] DRAM0_DM[1] DRAM0_DM[0] DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[13] DRAM1_A[12] DRAM1_A[11] DRAM1_A[10] DRAM1_A[9] DRAM1_A[8] DRAM1_A[7] DRAM1_A[6] DRAM1_A[5] DRAM1_A[4] DRAM1_A[3] DRAM1_A[2] DRAM1_A[1] DRAM1_A[0] DRAM1_BA[1] DRAM1_BA[0] DRAM1_DM[3] DRAM1_DM[2] DRAM1_DM[1] DRAM1_DM[0] SO0_ACLK SO0_CLK SO0_LRCLK SO0_DATA1 SO0_DATA2 SO0_DATA3 SO0_DATA4 SO0_DATA5 SO0_SPDIF SO1_ACLK SO1_CLK SO1_LRCLK SO1_DATA1 SO1_DATA2 SO1_DATA3 SO1_DATA4 SO1_DATA5 SO1_SPDIF HDMI_PDB VO0_CLK VO0_P[23] VO0_P[22] VO0_P[21] VO0_P[20] VO0_P[19] VO0_P[18] VO0_P[17] VO0_P[16] VO0_P[15] VO0_P[14] VO0_P[13] VO0_P[12] VO0_P[11] VO0_P[10] VO0_P[9] VO0_P[8] VO0_P[7] VO0_P[6] VO0_P[5] VO0_P[4] VO0_P[3] VO0_P[2] VO0_P[1] VO0_P[0] VO0_VLD PCI_AD[31] PCI_AD[30] PCI_CBEB[3] PCI_CBEB[2] PCI_CBEB[1] PCI_CBEB[0] PCI_PAR PCI_FRAMEB PCI_TRDYB PCI_IRDYB PCI_STOPB PCI_DEVSELB PCI_INTAB PB_A[24] PB_A[23] PB_A[22] PB_A[21] PB_A[20] PB_A[19] PB_A[18] PB_A[17] PB_A[16] PB_CSB[3] PB_CSB[2] PB_CSB[1] PB_CSB[0] PB_RDB PB_WRB PB_ALE PB_DMACKB PB_DIRB IDE_HIORN IDE_HIOWN IDE_DACKN IDE_HA[2] IDE_HA[1] IDE_HA[0] IDE_CS0N IDE_CS1N IDE_HD[15] IDE_HD[14] IDE_HD[13] IDE_HD[12] IDE_HD[11] IDE_HD[10] IDE_HD[9] IDE_HD[8] IDE_HD[7] IDE_HD[6] IDE_HD[5] IDE_HD[4] IDE_HD[3] IDE_HD[2] IDE_HD[1] IDE_HD[0] ETH_TXCLK ETH_TX_EN ETH_TXD[3] ETH_TXD[2] ETH_TXD[1] ETH_TXD[0] ETH_RXCLK ETH_RX_DV ETH_RX_ER ETH_RXD[3] ETH_RXD[2] ETH_RXD[1] ETH_RXD[0] ETH_CRS ETH_COL ETH_MDC ETH_MDIO ETH_MDINTB ETH_GPIO[15] ETH_GPIO[14] ETH_GPIO[13] ETH_GPIO[12] ETH_GPIO[11] ETH_GPIO[10] ETH_GPIO[9] ETH_GPIO[8] ETH_GPIO[7] ETH_GPIO[6] ETH_GPIO[5] ETH_GPIO[4] ETH_GPIO[3] ETH_GPIO[2] ETH_GPIO[1] ETH_GPIO[0] UART0_RX UART0_CTS UART0_DSR UART0_DCD UART0_TX UART0_RTS UART0_DTR UART1_RX UART1_CTS UART1_DSR UART1_DCD UART1_TX UART1_RTS UART1_DTR SCARD_RST SCARD_CLK SCARD_FCB SCARD_IO SCARD_CTL[2] SCARD_CTL[1] SCARD_CTL[0] RTC_XTAL_OUT RTC_RING RTC_CLK_OUT XTAL_OUT RCLK1_XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT GPIO[13] GPIO[12] GPIO[11] GPIO[10] GPIO[9] GPIO[8] GPIO[7] GPIO[6] 
r1 = 1.25 * Tcyc		#     95.00 ns

# Timeplate InOut  Group 0

PINS DRAM0_DQ[31] DRAM0_DQ[30] DRAM0_DQ[29] DRAM0_DQ[28] DRAM0_DQ[27] DRAM0_DQ[26] DRAM0_DQ[25] DRAM0_DQ[24] DRAM0_DQ[23] DRAM0_DQ[22] DRAM0_DQ[21] DRAM0_DQ[20] DRAM0_DQ[19] DRAM0_DQ[18] DRAM0_DQ[17] DRAM0_DQ[16] DRAM0_DQ[15] DRAM0_DQ[14] DRAM0_DQ[13] DRAM0_DQ[12] DRAM0_DQ[11] DRAM0_DQ[10] DRAM0_DQ[9] DRAM0_DQ[8] DRAM0_DQ[7] DRAM0_DQ[6] DRAM0_DQ[5] DRAM0_DQ[4] DRAM0_DQ[3] DRAM0_DQ[2] DRAM0_DQ[1] DRAM0_DQ[0] DRAM1_DQ[31] DRAM1_DQ[30] DRAM1_DQ[29] DRAM1_DQ[28] DRAM1_DQ[27] DRAM1_DQ[26] DRAM1_DQ[25] DRAM1_DQ[24] DRAM1_DQ[23] DRAM1_DQ[22] DRAM1_DQ[21] DRAM1_DQ[20] DRAM1_DQ[19] DRAM1_DQ[18] DRAM1_DQ[17] DRAM1_DQ[16] DRAM1_DQ[15] DRAM1_DQ[14] DRAM1_DQ[13] DRAM1_DQ[12] DRAM1_DQ[11] DRAM1_DQ[10] DRAM1_DQ[9] DRAM1_DQ[8] DRAM1_DQ[7] DRAM1_DQ[6] DRAM1_DQ[5] DRAM1_DQ[4] DRAM1_DQ[3] DRAM1_DQ[2] DRAM1_DQ[1] DRAM1_DQ[0] HDMI_DSCL HDMI_DSDA PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_IDSEL[0] PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] 
#d1 = 0.55 * Tcyc		#     55.00 ns
d1 = 0.00 * Tcyc		#     55.00 ns
r1 = 1.25 * Tcyc		#     95.00 ns

#####################################
###  Equations for SCAN PINS      ###
#####################################
PINS PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] 
r1 = 0.95 * Tcyc		#     95.00 ns

PINS GPIO[15] GPIO[14]
r1 = 1.25 * Tcyc		#     95.00 ns


PINS PB_AD[15] PB_AD[14] PB_AD[13] PB_AD[12] PB_AD[11] PB_AD[10] PB_AD[9] PB_AD[8] PB_AD[7] PB_AD[6] PB_AD[5] PB_AD[4] PB_AD[3] PB_AD[2] PB_AD[1] PB_AD[0] PB_A[15] PB_A[14] PB_A[13] PB_A[12] PB_A[11] PB_A[10] PB_A[9] PB_A[8] PB_A[7] PB_A[6] PB_A[5] PB_A[4] PB_A[3] PB_A[2] PB_A[1] PB_A[0]
d1 = 0.05 * Tcyc		#      5.00 ns


##########################################################
#    Equation Set scan x3                                #
##########################################################
EQNSET 2 "scanx3"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "scanx3"

period =  3.0 * Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
d1 = 0.00 * Tcyc			#   0.00 ns
d3 = 0.00 * Tcyc			#   0.00 ns
d4 = 0.00 * Tcyc + 1 * Tcyc	#   0.00 ns
d2 = 0.00 * Tcyc + 2 * Tcyc	#   0.00 ns

PINS USB20_XI
d1 = 0.00 * Tcyc			#   0.00 ns
d3 = 0.00 * Tcyc			#   0.00 ns
d4 = 0.00 * Tcyc + 1 * Tcyc	#   0.00 ns
d2 = 0.00 * Tcyc + 2 * Tcyc	#   0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc			#   0.00 ns
r2 = 0.00 * Tcyc			#   0.00 ns
r3 = 0.00 * Tcyc + 1 * Tcyc	#   0.00 ns
r4 = 0.00 * Tcyc + 2 * Tcyc	#   0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc			#   0.00 ns
d3 = 0.00 * Tcyc			#   0.00 ns
d4 = 0.00 * Tcyc + 1 * Tcyc	#   0.00 ns
d2 = 0.00 * Tcyc + 2 * Tcyc	#   0.00 ns

#####################################
###  Equations for NON-SCAN PINS  ###
#####################################

# Timplate Input  Group 0

PINS DRAM0_DQS[3] DRAM0_DQS[2] DRAM0_DQS[1] DRAM0_DQS[0] DRAM1_DQS[3] DRAM1_DQS[2] DRAM1_DQS[1] DRAM1_DQS[0] TS0_IN_CLK TS0_IN_VLD TS0_IN_SYNC TS0_IN_D[7] TS0_IN_D[6] TS0_IN_D[4] TS0_IN_D[3] TS0_IN_D[2] TS0_IN_D[0] TS1_IN_CLK TS1_IN_VLD TS1_IN_SYNC TS1_IN_D[7] TS1_IN_D[6] TS1_IN_D[5] TS1_IN_D[4] TS1_IN_D[3] TS1_IN_D[2] TS1_IN_D[0] TDMX_GPIO[1] TDMX_GPIO[0] SI0_SPDIF SI0_DATA SI0_CLK SI0_LRCLK SI1_SPDIF SI1_DATA SI1_CLK SI1_LRCLK HDMI_MSEN HDMI_HPD VI0_CLK VI0_P[31] VI0_P[30] VI0_P[29] VI0_P[28] VI0_P[27] VI0_P[26] VI0_P[25] VI0_P[24] VI0_P[23] VI0_P[22] VI0_P[21] VI0_P[20] VI0_P[19] VI0_P[18] VI0_P[17] VI0_P[16] VI0_P[15] VI0_P[14] VI0_P[13] VI0_P[12] VI0_P[11] VI0_P[10] VI0_P[9] VI0_P[8] VI0_P[7] VI0_P[6] VI0_P[5] VI0_P[4] VI0_P[3] VI0_P[2] VI0_P[1] VI0_P[0] VI0_VLD VI0_HS VI0_VS VI1_CLK VI1_P[7] VI1_P[6] VI1_P[5] VI1_P[4] VI1_P[3] VI1_P[2] VI1_P[1] VI1_P[0] VI1_VLD VI1_HS VI1_VS VI2_CLK VI2_VLD VI2_HS VI2_VS VO0_HS VO0_VS PCI_REQB[3] PCI_REQB[2] PCI_REQB[1] PCI_REQB[0] PB_IORDY PB_DMARQ IDE_IORDY IDE_INTRQ IDE_DMARQ IDE_NPCBLID JTAG_UART RTC_XTAL_IN RTC_TEST RTC_XTAL_DISC RTC_CLK_IN XTAL_IN XTAL_BUF XTAL_DISC RCLK1_XTAL_IN TEST 
d1 = 0.05 * Tcyc		#      5.00 ns
d3 = 0.05 * Tcyc		#      5.00 ns
d4 = 0.05 * Tcyc + 1 * Tcyc	#      5.00 ns
d2 = 0.05 * Tcyc + 2 * Tcyc	#      5.00 ns

# Timplate Input  Group 1

PINS TS0_IN_D[5] TS0_IN_D[1] TS1_IN_D[1] PCI_CLK VCXO0_IN VCXO1_IN RCLK0_IN GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] 
d1 = 0.30 * Tcyc		#     45.00 ns
d3 = 0.85 * Tcyc		#     55.00 ns
d4 = 0.30 * Tcyc		#     45.00 ns
d2 = 0.85 * Tcyc		#     55.00 ns
d5 = 0.30 * Tcyc + 1 * Tcyc	#     45.00 ns
d7 = 0.85 * Tcyc + 1 * Tcyc	#     55.00 ns
d8 = 0.30 * Tcyc + 2 * Tcyc	#     45.00 ns
d6 = 0.85 * Tcyc + 2 * Tcyc	#     55.00 ns

# Timplate Input  Group 2

PINS RESETB 
d1 = 0.30 * Tcyc		#     45.00 ns
d3 = 0.85 * Tcyc		#     55.00 ns
d4 = 0.30 * Tcyc		#     45.00 ns
d2 = 0.85 * Tcyc		#     55.00 ns
d5 = 0.30 * Tcyc + 1 * Tcyc	#     45.00 ns
d7 = 0.85 * Tcyc + 1 * Tcyc	#     55.00 ns
d8 = 0.30 * Tcyc + 2 * Tcyc	#     45.00 ns
d6 = 0.85 * Tcyc + 2 * Tcyc	#     55.00 ns

# Timplate Output Group 0

PINS DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[13] DRAM0_A[12] DRAM0_A[11] DRAM0_A[10] DRAM0_A[9] DRAM0_A[8] DRAM0_A[7] DRAM0_A[6] DRAM0_A[5] DRAM0_A[4] DRAM0_A[3] DRAM0_A[2] DRAM0_A[1] DRAM0_A[0] DRAM0_BA[1] DRAM0_BA[0] DRAM0_DM[3] DRAM0_DM[2] DRAM0_DM[1] DRAM0_DM[0] DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[13] DRAM1_A[12] DRAM1_A[11] DRAM1_A[10] DRAM1_A[9] DRAM1_A[8] DRAM1_A[7] DRAM1_A[6] DRAM1_A[5] DRAM1_A[4] DRAM1_A[3] DRAM1_A[2] DRAM1_A[1] DRAM1_A[0] DRAM1_BA[1] DRAM1_BA[0] DRAM1_DM[3] DRAM1_DM[2] DRAM1_DM[1] DRAM1_DM[0] SO0_ACLK SO0_CLK SO0_LRCLK SO0_DATA1 SO0_DATA2 SO0_DATA3 SO0_DATA4 SO0_DATA5 SO0_SPDIF SO1_ACLK SO1_CLK SO1_LRCLK SO1_DATA1 SO1_DATA2 SO1_DATA3 SO1_DATA4 SO1_DATA5 SO1_SPDIF HDMI_PDB VO0_CLK VO0_P[23] VO0_P[22] VO0_P[21] VO0_P[20] VO0_P[19] VO0_P[18] VO0_P[17] VO0_P[16] VO0_P[15] VO0_P[14] VO0_P[13] VO0_P[12] VO0_P[11] VO0_P[10] VO0_P[9] VO0_P[8] VO0_P[7] VO0_P[6] VO0_P[5] VO0_P[4] VO0_P[3] VO0_P[2] VO0_P[1] VO0_P[0] VO0_VLD PCI_AD[31] PCI_AD[30] PCI_CBEB[3] PCI_CBEB[2] PCI_CBEB[1] PCI_CBEB[0] PCI_PAR PCI_FRAMEB PCI_TRDYB PCI_IRDYB PCI_STOPB PCI_DEVSELB PCI_INTAB PB_A[24] PB_A[23] PB_A[22] PB_A[21] PB_A[20] PB_A[19] PB_A[18] PB_A[17] PB_A[16] PB_CSB[3] PB_CSB[2] PB_CSB[1] PB_CSB[0] PB_RDB PB_WRB PB_ALE PB_DMACKB PB_DIRB IDE_HIORN IDE_HIOWN IDE_DACKN IDE_HA[2] IDE_HA[1] IDE_HA[0] IDE_CS0N IDE_CS1N IDE_HD[15] IDE_HD[14] IDE_HD[13] IDE_HD[12] IDE_HD[11] IDE_HD[10] IDE_HD[9] IDE_HD[8] IDE_HD[7] IDE_HD[6] IDE_HD[5] IDE_HD[4] IDE_HD[3] IDE_HD[2] IDE_HD[1] IDE_HD[0] ETH_TXCLK ETH_TX_EN ETH_TXD[3] ETH_TXD[2] ETH_TXD[1] ETH_TXD[0] ETH_RXCLK ETH_RX_DV ETH_RX_ER ETH_RXD[3] ETH_RXD[2] ETH_RXD[1] ETH_RXD[0] ETH_CRS ETH_COL ETH_MDC ETH_MDIO ETH_MDINTB ETH_GPIO[15] ETH_GPIO[14] ETH_GPIO[13] ETH_GPIO[12] ETH_GPIO[11] ETH_GPIO[10] ETH_GPIO[9] ETH_GPIO[8] ETH_GPIO[7] ETH_GPIO[6] ETH_GPIO[5] ETH_GPIO[4] ETH_GPIO[3] ETH_GPIO[2] ETH_GPIO[1] ETH_GPIO[0] UART0_RX UART0_CTS UART0_DSR UART0_DCD UART0_TX UART0_RTS UART0_DTR UART1_RX UART1_CTS UART1_DSR UART1_DCD UART1_TX UART1_RTS UART1_DTR SCARD_RST SCARD_CLK SCARD_FCB SCARD_IO SCARD_CTL[2] SCARD_CTL[1] SCARD_CTL[0] RTC_XTAL_OUT RTC_RING RTC_CLK_OUT XTAL_OUT RCLK1_XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT GPIO[13] GPIO[12] GPIO[11] GPIO[10] GPIO[9] GPIO[8] GPIO[7] GPIO[6] 
#r1 = 0.95 * Tcyc		#     95.00 ns
#r2 = 0.95 * Tcyc		#     95.00 ns
#r3 = 0.95 * Tcyc + 1 * Tcyc	#     95.00 ns
#r4 = 0.95 * Tcyc + 2 * Tcyc	#     95.00 ns
r1 = 1.25 * Tcyc		#     95.00 ns
r2 = 1.25 * Tcyc		#     95.00 ns
r3 = 1.25 * Tcyc + 1 * Tcyc	#     95.00 ns
r4 = 1.25 * Tcyc + 2 * Tcyc	#     95.00 ns

# Timplate InOut  Group 0

PINS DRAM0_DQ[31] DRAM0_DQ[30] DRAM0_DQ[29] DRAM0_DQ[28] DRAM0_DQ[27] DRAM0_DQ[26] DRAM0_DQ[25] DRAM0_DQ[24] DRAM0_DQ[23] DRAM0_DQ[22] DRAM0_DQ[21] DRAM0_DQ[20] DRAM0_DQ[19] DRAM0_DQ[18] DRAM0_DQ[17] DRAM0_DQ[16] DRAM0_DQ[15] DRAM0_DQ[14] DRAM0_DQ[13] DRAM0_DQ[12] DRAM0_DQ[11] DRAM0_DQ[10] DRAM0_DQ[9] DRAM0_DQ[8] DRAM0_DQ[7] DRAM0_DQ[6] DRAM0_DQ[5] DRAM0_DQ[4] DRAM0_DQ[3] DRAM0_DQ[2] DRAM0_DQ[1] DRAM0_DQ[0] DRAM1_DQ[31] DRAM1_DQ[30] DRAM1_DQ[29] DRAM1_DQ[28] DRAM1_DQ[27] DRAM1_DQ[26] DRAM1_DQ[25] DRAM1_DQ[24] DRAM1_DQ[23] DRAM1_DQ[22] DRAM1_DQ[21] DRAM1_DQ[20] DRAM1_DQ[19] DRAM1_DQ[18] DRAM1_DQ[17] DRAM1_DQ[16] DRAM1_DQ[15] DRAM1_DQ[14] DRAM1_DQ[13] DRAM1_DQ[12] DRAM1_DQ[11] DRAM1_DQ[10] DRAM1_DQ[9] DRAM1_DQ[8] DRAM1_DQ[7] DRAM1_DQ[6] DRAM1_DQ[5] DRAM1_DQ[4] DRAM1_DQ[3] DRAM1_DQ[2] DRAM1_DQ[1] DRAM1_DQ[0] HDMI_DSCL HDMI_DSDA PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_IDSEL[0] PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] 
d1 = 0.00 * Tcyc		#     55.00 ns
d3 = 0.00 * Tcyc		#     55.00 ns
d4 = 0.00 * Tcyc + 1 * Tcyc	#     55.00 ns
d2 = 0.00 * Tcyc + 2 * Tcyc	#     55.00 ns
r1 = 1.25 * Tcyc		#     95.00 ns
r2 = 1.25 * Tcyc		#     95.00 ns
r3 = 1.25 * Tcyc + 1 * Tcyc	#     95.00 ns
r4 = 1.25 * Tcyc + 2 * Tcyc	#     95.00 ns

#####################################
###  Equations for SCAN PINS      ###
#####################################
PINS PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0]
r1 = 0.95 * Tcyc		#     95.00 ns
r2 = 0.95 * Tcyc		#     95.00 ns
r3 = 0.95 * Tcyc + 1 * Tcyc	#     95.00 ns
r4 = 0.95 * Tcyc + 2 * Tcyc	#     95.00 ns

PINS GPIO[15] GPIO[14]
r1 = 1.30 * Tcyc		#     95.00 ns
r2 = 1.30 * Tcyc		#     95.00 ns
r3 = 1.30 * Tcyc + 1 * Tcyc	#     95.00 ns
r4 = 1.30 * Tcyc + 2 * Tcyc	#     95.00 ns

PINS PB_AD[15] PB_AD[14] PB_AD[13] PB_AD[12] PB_AD[11] PB_AD[10] PB_AD[9] PB_AD[8] PB_AD[7] PB_AD[6] PB_AD[5] PB_AD[4] PB_AD[3] PB_AD[2] PB_AD[1] PB_AD[0] PB_A[15] PB_A[14] PB_A[13] PB_A[12] PB_A[11] PB_A[10] PB_A[9] PB_A[8] PB_A[7] PB_A[6] PB_A[5] PB_A[4] PB_A[3] PB_A[2] PB_A[1] PB_A[0] 
d1 = 0.05 * Tcyc		#      5.00 ns
d3 = 0.05 * Tcyc		#      5.00 ns
d4 = 0.05 * Tcyc + 1 * Tcyc	#      5.00 ns
d2 = 0.05 * Tcyc + 2 * Tcyc	#      5.00 ns

##########################################################
#    Equation Set - bist                                 #
##########################################################
EQNSET 3 "bist"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "bist"

#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns


PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VI0_CLK VI1_CLK VI2_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

#PINS tg1I1
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I3
PINS RESETB PCI_REQB[0]
#d1 = 0.57 * Tcyc	# 8.10ns
d1 = 0.00 * Tcyc	# 8.10ns

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
#r1 = 0.25 * Tcyc	# 0.10ns
r1 = 0.15 * Tcyc	# 0.10ns

PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 = 0.25 * Tcyc	# 0.10ns

PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] 
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
#r1 = 0.90 * Tcyc	# 7.60ns
r1 = 1.00 * Tcyc	# 7.60ns

PINS PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.70 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 =  0.50 * Tcyc	# 7.60ns

#PINS tg1B8
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B9
PINS PCI_CBEB[2]
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B10
PINS PCI_IDSEL[0]
d1 = 0.65 * Tcyc	# 9.20ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

######################################
#    maskout signals                 #
######################################
PINS RCLK1_XTAL_OUT
r1 = 0.50 * Tcyc	# 7.10ns

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.00 * Tcyc	# 0.00ns

PINS XTAL_BUF 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns


##########################################################
#    Equation Set - serial flash                         #
##########################################################
EQNSET 4 "serial_flash"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "serial_flash"

#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0
d1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM0_VREFSSTL1
d1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM0_VREFSSTL23
d1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM1_VREFSSTL0
d1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM1_VREFSSTL1
d1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM1_VREFSSTL23
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns


#PINS tg1I0
PINS XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#d1 = 0.57 * Tcyc	# 8.10ns
d1 = 0.00 * Tcyc	# 8.10ns

#PINS tg1I2
PINS PCI_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc		#      0.00 ns
d2 = 0.85 * Tcyc		#      0.00 ns

#PINS tg1B3
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 = 0.80 * Tcyc	# 7.60ns

#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B5
PINS PCI_CBEB[2]
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B6
PINS PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns

#PINS tg1B7
PINS PCI_IDSEL[0]
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns


##########################################################
#    Equation Set dac                                    #
##########################################################
EQNSET 5 "dac"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency          [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

#|-------------------------------|
#|   Timing Set 1 :: dac_setup   |
#|-------------------------------|

TIMINGSET 1 "dac"
#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns


PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VI0_CLK VI1_CLK VI2_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

#PINS tg1I1
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I3
PINS RESETB PCI_REQB[0]
#d1 = 0.57 * Tcyc	# 8.10ns
d1 = 0.00 * Tcyc	# 8.10ns

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 = 0.25 * Tcyc	# 0.10ns

PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 = 0.25 * Tcyc	# 0.10ns

PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] 
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 = 0.90 * Tcyc	# 7.60ns

PINS PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.70 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 =  0.50 * Tcyc	# 7.60ns

#PINS tg1B8
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B9
PINS PCI_CBEB[2]
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B10
PINS PCI_IDSEL[0]
d1 = 0.65 * Tcyc	# 9.20ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

######################################
#    maskout signals                 #
######################################
PINS RCLK1_XTAL_OUT
r1 = 0.50 * Tcyc	# 7.10ns

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.00 * Tcyc	# 0.00ns

PINS XTAL_BUF 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns



##########################################################
#    Equation Set scan                                   #
##########################################################
EQNSET 6 "pll"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency          [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

#|-------------------------------|
#|   Timing Set 1 :: dac_setup   |
#|-------------------------------|

TIMINGSET 1 "pll"
#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns


PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VI0_CLK VI1_CLK VI2_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

#PINS tg1I1
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I3
PINS RESETB PCI_REQB[0]
#d1 = 0.57 * Tcyc	# 8.10ns
d1 = 0.00 * Tcyc	# 8.10ns

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 = 0.25 * Tcyc	# 0.10ns

PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 = 0.25 * Tcyc	# 0.10ns

PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] 
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 = 0.90 * Tcyc	# 7.60ns

PINS PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.70 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 =  0.50 * Tcyc	# 7.60ns

#PINS tg1B8
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B9
PINS PCI_CBEB[2]
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B10
PINS PCI_IDSEL[0]
d1 = 0.65 * Tcyc	# 9.20ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

######################################
#    maskout signals                 #
######################################
PINS RCLK1_XTAL_OUT
r1 = 0.50 * Tcyc	# 7.10ns

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.00 * Tcyc	# 0.00ns

PINS XTAL_BUF 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns


##########################################################
#    Equation Set - serial flash bist                    #
##########################################################
EQNSET 7 "serial_flash_bist"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "serial_flash_bist"

#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns


#PINS tg1I0
PINS XTAL_IN XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#d1 = 0.57 * Tcyc	# 8.10ns
d1 = 0.00 * Tcyc	# 8.10ns

#PINS tg1I2
PINS PCI_CLK RCLK1_XTAL_IN  VI0_CLK  VI1_CLK  VI2_CLK  VCXO0_IN  VCXO1_IN 
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc		#      0.00 ns
d2 = 0.85 * Tcyc		#      0.00 ns

#PINS tg1B3
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 = 0.80 * Tcyc	# 7.60ns

#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B5
PINS PCI_CBEB[2]
d1 = 0.64 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B6
PINS GPIO[13] PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.14 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.14 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns

PINS PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.14 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns

PINS PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.14 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns

PINS PCI_IDSEL[0]
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.70ns
r1 = 0.25 * Tcyc	# 7.70ns

##########################################################
#    Equation Set serialization                          #
##########################################################
EQNSET 8 "serialization"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "serialization"

#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0
e1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM0_VREFSSTL1
e1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM0_VREFSSTL23
e1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM1_VREFSSTL0
e1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM1_VREFSSTL1
e1 = 0.00 * Tcyc		#      0.00 ns

PINS DRAM1_VREFSSTL23
e1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XI
e1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XO
e4 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
e1 = 0.00 * Tcyc		#      0.00 ns


#PINS tg1I0
PINS XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
e1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#e1 = 0.57 * Tcyc	# 8.10ns
e1 = 0.00 * Tcyc	# 8.10ns

#PINS tg1I2
PINS PCI_CLK
e1 = 0.35 * Tcyc	# 0.00ns
e2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
e1 = 0.35 * Tcyc		#      0.00 ns
e2 = 0.85 * Tcyc		#      0.00 ns

#PINS tg1B3
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
e1 = 0.64 * Tcyc	# 9.10ns
#d3 = 0.00 * Tcyc	# 0.00ns
#e4 = 0.54 * Tcyc	# 7.60ns
e4 = 0.80 * Tcyc	# 7.60ns

#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
e1 = 0.64 * Tcyc	# 9.10ns
#d3 = 0.00 * Tcyc	# 0.00ns
e4 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B5
PINS PCI_CBEB[2]
e1 = 0.64 * Tcyc	# 9.10ns
#d3 = 0.00 * Tcyc	# 0.00ns
e4 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B6
PINS PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
e1 = 0.00 * Tcyc	# 0.00ns
#d3 = 0.00 * Tcyc	# 0.00ns
#e4 = 0.54 * Tcyc	# 7.70ns
e4 = 0.25 * Tcyc	# 7.70ns

#PINS tg1B7
PINS PCI_IDSEL[0]
e1 = 0.00 * Tcyc	# 0.00ns
#d3 = 0.00 * Tcyc	# 0.00ns
#e4 = 0.54 * Tcyc	# 7.70ns
e4 = 0.25 * Tcyc	# 7.70ns


##########################################################
#    Equation Set dram bist                              #
##########################################################
EQNSET 9 "dram_bist"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "dram_bist"

#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns


PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VI0_CLK VI1_CLK VI2_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

#PINS tg1I1
PINS VCXO0_IN VCXO1_IN RCLK1_XTAL_IN PCI_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

PINS XTAL_IN XTAL_DISC TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I3
PINS RESETB PCI_REQB[0]
#d1 = 0.57 * Tcyc	# 8.10ns
d1 = 0.00 * Tcyc	# 8.10ns

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
#r1 = 0.25 * Tcyc	# 0.10ns
r1 = 0.15 * Tcyc	# 0.10ns

PINS PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
#r1 = 0.25 * Tcyc	# 0.10ns
r1 = 0.20 * Tcyc	# 0.10ns

PINS PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
#r1 = 0.25 * Tcyc	# 0.10ns
r1 = 0.15 * Tcyc	# 0.10ns

PINS PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 = 0.25 * Tcyc	# 0.10ns

PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] 
d1 = 0.60 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
#r1 = 0.90 * Tcyc	# 7.60ns
r1 = 1.00 * Tcyc	# 7.60ns

PINS PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.60 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.54 * Tcyc	# 7.60ns
r1 =  0.50 * Tcyc	# 7.60ns

#PINS tg1B8
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
d1 = 0.60 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B9
PINS PCI_CBEB[2]
d1 = 0.60 * Tcyc	# 9.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B10
PINS PCI_IDSEL[0]
d1 = 0.60 * Tcyc	# 9.20ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#################################################
###   09/23/2006   DRAM0, DRAM1               ###
#################################################
PINS DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[0] DRAM0_A[1] DRAM0_A[2] DRAM0_A[3] DRAM0_A[4] DRAM0_A[5] DRAM0_A[6] DRAM0_A[7] DRAM0_A[8] DRAM0_A[9] DRAM0_A[10] DRAM0_A[11] DRAM0_A[12] DRAM0_A[13] DRAM0_BA[0] DRAM0_BA[1] DRAM0_DM[0] DRAM0_DM[1] DRAM0_DM[2] DRAM0_DM[3] 
r1 = 0.25 * Tcyc	# 0.00ns

PINS DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[0] DRAM1_A[1] DRAM1_A[2] DRAM1_A[3] DRAM1_A[4] DRAM1_A[5] DRAM1_A[6] DRAM1_A[7] DRAM1_A[8] DRAM1_A[9] DRAM1_A[10] DRAM1_A[11] DRAM1_A[12] DRAM1_A[13] DRAM1_BA[0] DRAM1_BA[1] DRAM1_DM[0] DRAM1_DM[1] DRAM1_DM[2] DRAM1_DM[3]
r1 = 0.25 * Tcyc	# 0.00ns

#PINS tg1B6
PINS DRAM0_DQS[0] DRAM0_DQS[1] DRAM0_DQS[2] DRAM0_DQS[3] DRAM0_DQ[0] DRAM0_DQ[1] DRAM0_DQ[2] DRAM0_DQ[3] DRAM0_DQ[4] DRAM0_DQ[5] DRAM0_DQ[6] DRAM0_DQ[7] DRAM0_DQ[8] DRAM0_DQ[9] DRAM0_DQ[10] DRAM0_DQ[11] DRAM0_DQ[12] DRAM0_DQ[13] DRAM0_DQ[14] DRAM0_DQ[15] DRAM0_DQ[16] DRAM0_DQ[17] DRAM0_DQ[18] DRAM0_DQ[19] DRAM0_DQ[20] DRAM0_DQ[21] DRAM0_DQ[22] DRAM0_DQ[23] DRAM0_DQ[24] DRAM0_DQ[25] DRAM0_DQ[26] DRAM0_DQ[27] DRAM0_DQ[28] DRAM0_DQ[29] DRAM0_DQ[30] DRAM0_DQ[31] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns

PINS DRAM1_DQS[0] DRAM1_DQS[1] DRAM1_DQS[2] DRAM1_DQS[3] DRAM1_DQ[0] DRAM1_DQ[1] DRAM1_DQ[2] DRAM1_DQ[3] DRAM1_DQ[4] DRAM1_DQ[5] DRAM1_DQ[6] DRAM1_DQ[7] DRAM1_DQ[8] DRAM1_DQ[9] DRAM1_DQ[10] DRAM1_DQ[11] DRAM1_DQ[12] DRAM1_DQ[13] DRAM1_DQ[14] DRAM1_DQ[15] DRAM1_DQ[16] DRAM1_DQ[17] DRAM1_DQ[18] DRAM1_DQ[19] DRAM1_DQ[20] DRAM1_DQ[21] DRAM1_DQ[22] DRAM1_DQ[23] DRAM1_DQ[24] DRAM1_DQ[25] DRAM1_DQ[26] DRAM1_DQ[27] DRAM1_DQ[28] DRAM1_DQ[29] DRAM1_DQ[30] DRAM1_DQ[31]
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns

######################################
#    maskout signals                 #
######################################
PINS RCLK1_XTAL_OUT
r1 = 0.50 * Tcyc	# 7.10ns

PINS XTAL_OUT RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.00 * Tcyc	# 0.00ns

PINS XTAL_BUF 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns

##########################################################
#    12/06/06 atspeed bist_5us                           #
#    - RCLK1_XTAL_IN on for 5us first                    #
#    - RCLK0_IN 1 = NRZ 1.                               #
#               0 = RZ                                   #
##########################################################
EQNSET 12 "atspeed_bist_5us"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "atspeed_bist_5us"

#
# Period = 12.50 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23 USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns


PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#PINS tg1I0
PINS XTAL_IN XTAL_DISC VCXO0_IN VCXO1_IN RCLK1_XTAL_IN TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3] PCI_CLK
d1 = 0.00 * Tcyc	# 0.00ns

###########################################
##  added VIx_CLK (need to run 2x freq)  ##
###########################################
PINS VI0_CLK VI1_CLK VI2_CLK
#d1 = 0.00 * Tcyc		#      0.00 ns
#d2 = 0.25 * Tcyc		#      0.00 ns
#d3 = 0.50 * Tcyc		#      0.00 ns
#d4 = 0.75 * Tcyc		#      0.00 ns
d1 = 0.35 * Tcyc		#      0.00 ns
d2 = 0.60 * Tcyc		#      0.00 ns
d3 = 0.85 * Tcyc		#      0.00 ns
d4 = 1.10 * Tcyc		#      0.00 ns

#PINS tg1I1
PINS RCLK0_IN
#d1 = 0.00 * Tcyc	# 0.00ns
#d2 = 0.50 * Tcyc	# 6.25ns
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 6.25ns

#PINS tg1I2
PINS RESETB PCI_REQB[0]
#d1 = 0.08 * Tcyc	# 1.00ns
d1 = 0.40 * Tcyc	# 1.00ns

#PINS tg1O3
PINS XTAL_OUT RCLK1_XTAL_OUT
r1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1O4
PINS RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.28 * Tcyc	# 3.44ns

#PINS tg1B5
PINS XTAL_BUF PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.01 * Tcyc	# 0.10ns

PINS PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 1.30 * Tcyc	# 0.10ns

########################################
##  fixed                             ##
########################################

PINS PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] 
#d1 = 0.00 * Tcyc	# 0.00ns
#d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.00 * Tcyc	# 0.10ns
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 1.20 * Tcyc	# 0.10ns
r1 = 1.70 * Tcyc	# 0.10ns


PINS PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.01 * Tcyc	# 0.10ns
r1 =  1.30 * Tcyc	# 0.10ns

PINS PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 0.10ns

#PINS tg1B6
PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] 
d1 = 0.16 * Tcyc	# 2.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.04 * Tcyc	# 0.50ns
r1 = 0.30 * Tcyc	# 0.50ns

PINS PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.16 * Tcyc	# 2.00ns
d3 = 0.00 * Tcyc	# 0.00ns
#r1 = 0.04 * Tcyc	# 0.50ns
r1 = 0.50 * Tcyc	# 0.50ns

#PINS tg1B7
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[2] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB
d1 = 0.16 * Tcyc	# 2.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 11.88ns

#PINS tg1B8
PINS PCI_IDSEL[0]
d1 = 0.17 * Tcyc	# 2.10ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 11.88ns

###########################################
##  added GPIO signals                   ##
###########################################
PINS GPIO[0]
d1 = 0.00 * Tcyc		#      0.00 ns

PINS GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15]
r1 = 0.00 * Tcyc		#      0.00 ns


##########################################################
#    Equation Set for display_func (Horizontal Noise)    #
##########################################################
EQNSET 13 "display_func"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "display_func"

#
# Period = 40.00 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS VO0_VLD 
#r1 = 0.00 * Tcyc		#      0.00 ns
#r2 = 0.20 * Tcyc		#      0.00 ns
#r3 = 0.53 * Tcyc		#      0.00 ns
#r4 = 0.86 * Tcyc		#      0.00 ns
r1 = 0.05 * Tcyc		#      0.00 ns
r2 = 0.25 * Tcyc		#      0.00 ns
r3 = 0.58 * Tcyc		#      0.00 ns
r4 = 0.91 * Tcyc		#      0.00 ns

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
r1 = 0.00 * Tcyc		#      0.00 ns


PINS USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

PINS VI0_CLK VI1_CLK VI2_CLK
d1 = 0.00 * Tcyc		#      0.00 ns

PINS XTAL_IN XTAL_DISC VCXO0_IN VCXO1_IN TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I1
PINS RCLK0_IN RCLK1_XTAL_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 20.00ns

#PINS tg1I2
PINS RESETB PCI_REQB[0]
#d1 = 0.96 * Tcyc	# 38.50ns
d1 = 0.20 * Tcyc	# 38.50ns

#PINS tg1O3
PINS XTAL_OUT RCLK1_XTAL_OUT
r1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1O4
PINS RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.04 * Tcyc	# 1.40ns

#PINS tg1B5
PINS XTAL_BUF PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.00 * Tcyc	# 0.10ns

#PINS tg1B6
PINS PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31]
d1 = 0.24 * Tcyc	# 9.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.82 * Tcyc	# 33.00ns

#PINS tg1B7
PINS PCI_CBEB[0] PCI_CBEB[1] PCI_CBEB[3] PCI_IRDYB
d1 = 0.24 * Tcyc	# 9.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 38.00ns

#PINS tg1B8
PINS PCI_CBEB[2]
d1 = 0.24 * Tcyc	# 9.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 38.00ns

#PINS tg1B9
PINS PCI_PAR PCI_STOPB PCI_DEVSELB
d1 = 0.74 * Tcyc	# 29.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 38.00ns

#PINS tg1B10
PINS PCI_FRAMEB
d1 = 0.12 * Tcyc	# 4.60ns
d2 = 0.74 * Tcyc	# 29.60ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 38.00ns

#PINS tg1B11
PINS PCI_TRDYB
d1 = 0.57 * Tcyc	# 23.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.33 * Tcyc	# 13.00ns

#PINS tg1B12
PINS PCI_IDSEL[0]
d1 = 0.12 * Tcyc	# 4.60ns
d2 = 0.74 * Tcyc	# 29.60ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 38.00ns

##########################################################
#    Equation Set  (dram_func_M804q_070215_p)            #
##########################################################
EQNSET 14 "dram_func"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "dram_func"

#
# Period = 14.20 ns
#
period =  Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0 DRAM0_VREFSSTL1 DRAM0_VREFSSTL23 DRAM1_VREFSSTL0 DRAM1_VREFSSTL1 DRAM1_VREFSSTL23
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XI
d1 = 0.00 * Tcyc		#      0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc		#      0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc		#      0.00 ns

#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################
PINS VI0_CLK VI1_CLK VI2_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

#PINS tg1I0
PINS XTAL_IN XTAL_DISC VCXO0_IN VCXO1_IN RCLK1_XTAL_IN TEST PCI_REQB[1] PCI_REQB[2] PCI_REQB[3]
d1 = 0.00 * Tcyc	# 0.00ns

#PINS tg1I1
PINS RCLK0_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 7.10ns

#PINS tg1I2
PINS RESETB PCI_REQB[0]
d1 = 0.50 * Tcyc	# 3.10ns

#PINS tg1I3
PINS PCI_CLK
d1 = 0.76 * Tcyc	# 10.80ns

#PINS tg1O4
PINS XTAL_OUT RCLK1_XTAL_OUT DRAM0_CK DRAM0_CKB DRAM0_CKE DRAM0_SB DRAM0_RASB DRAM0_CASB DRAM0_WEB DRAM0_A[0] DRAM0_A[1] DRAM0_A[2] DRAM0_A[3] DRAM0_A[4] DRAM0_A[5] DRAM0_A[6] DRAM0_A[7] DRAM0_A[8] DRAM0_A[9] DRAM0_A[10] DRAM0_A[11] DRAM0_A[12] DRAM0_A[13] DRAM0_BA[0] DRAM0_BA[1] DRAM0_DM[0] DRAM0_DM[1] DRAM0_DM[2] DRAM0_DM[3] DRAM1_CK DRAM1_CKB DRAM1_CKE DRAM1_SB DRAM1_RASB DRAM1_CASB DRAM1_WEB DRAM1_A[0] DRAM1_A[1] DRAM1_A[2] DRAM1_A[3] DRAM1_A[4] DRAM1_A[5] DRAM1_A[6] DRAM1_A[7] DRAM1_A[8] DRAM1_A[9] DRAM1_A[10] DRAM1_A[11] DRAM1_A[12] DRAM1_A[13] DRAM1_BA[0] DRAM1_BA[1] DRAM1_DM[0] DRAM1_DM[1] DRAM1_DM[2] DRAM1_DM[3]
#r1 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 0.00ns

#PINS tg1O5
PINS RCLK0_OUT RCLK1_OUT RCLK2_OUT RCLK3_OUT
r1 = 0.70 * Tcyc	# 9.99ns

#PINS tg1B6
PINS XTAL_BUF PCI_INTAB PCI_IDSEL[1] PCI_IDSEL[2] PCI_IDSEL[3] PCI_GNTB[0] PCI_GNTB[1] PCI_GNTB[2] PCI_GNTB[3] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 1.10 * Tcyc	# 0.10ns

PINS PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB DRAM0_DQS[0] DRAM0_DQS[1] DRAM0_DQS[2] DRAM0_DQS[3] DRAM0_DQ[0] DRAM0_DQ[1] DRAM0_DQ[2] DRAM0_DQ[3] DRAM0_DQ[4] DRAM0_DQ[5] DRAM0_DQ[6] DRAM0_DQ[7] DRAM0_DQ[8] DRAM0_DQ[9] DRAM0_DQ[10] DRAM0_DQ[11] DRAM0_DQ[12] DRAM0_DQ[13] DRAM0_DQ[14] DRAM0_DQ[15] DRAM0_DQ[16] DRAM0_DQ[17] DRAM0_DQ[18] DRAM0_DQ[19] DRAM0_DQ[20] DRAM0_DQ[21] DRAM0_DQ[22] DRAM0_DQ[23] DRAM0_DQ[24] DRAM0_DQ[25] DRAM0_DQ[26] DRAM0_DQ[27] DRAM0_DQ[28] DRAM0_DQ[29] DRAM0_DQ[30] DRAM0_DQ[31] DRAM1_DQS[0] DRAM1_DQS[1] DRAM1_DQS[2] DRAM1_DQS[3] DRAM1_DQ[0] DRAM1_DQ[1] DRAM1_DQ[2] DRAM1_DQ[3] DRAM1_DQ[4] DRAM1_DQ[5] DRAM1_DQ[6] DRAM1_DQ[7] DRAM1_DQ[8] DRAM1_DQ[9] DRAM1_DQ[10] DRAM1_DQ[11] DRAM1_DQ[12] DRAM1_DQ[13] DRAM1_DQ[14] DRAM1_DQ[15] DRAM1_DQ[16] DRAM1_DQ[17] DRAM1_DQ[18] DRAM1_DQ[19] DRAM1_DQ[20] DRAM1_DQ[21] DRAM1_DQ[22] DRAM1_DQ[23] DRAM1_DQ[24] DRAM1_DQ[25] DRAM1_DQ[26] DRAM1_DQ[27] DRAM1_DQ[28] DRAM1_DQ[29] DRAM1_DQ[30] DRAM1_DQ[31]
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 1.25 * Tcyc	# 0.10ns

PINS PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] 
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 1.30 * Tcyc	# 0.10ns

#PINS tg1B7
PINS PCI_AD[0] PCI_AD[2] PCI_AD[8] PCI_AD[12] PCI_AD[18] PCI_AD[20] PCI_AD[21] PCI_AD[25] PCI_AD[26] PCI_AD[31] PCI_STOPB PCI_DEVSELB
d1 = 0.81 * Tcyc	# 11.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.51 * Tcyc	# 7.20ns

#PINS tg1B8
PINS PCI_AD[1] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[19] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_PAR PCI_TRDYB
d1 = 0.81 * Tcyc	# 11.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.60 * Tcyc	# 7.20ns

#PINS tg1B9
PINS PCI_CBEB[0] PCI_CBEB[2]
d1 = 0.81 * Tcyc	# 11.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns

#PINS tg1B10
PINS PCI_CBEB[1] PCI_CBEB[3] PCI_FRAMEB PCI_IRDYB PCI_IDSEL[0]
d1 = 0.81 * Tcyc	# 11.50ns
d3 = 0.00 * Tcyc	# 0.00ns
r1 = 0.95 * Tcyc	# 13.49ns


##########################################################
#    Equation Set                                        #
##########################################################
EQNSET 15 "serial_flash_x2"

#|--------------|
#|   Spec       |
#|--------------|
SPECS    # starts the declaration of the specs

Frequency    [MHZ]   # frequency for the test

#|--------------|
#|   Equations  |
#|--------------|
EQUATIONS

Tcyc = 1000/Frequency

TIMINGSET 1 "serial_flash_x2"

#
# Period = 12.50 ns, *** X2 mode actual period = 25.00 ns ***
#
period =  2.0 * Tcyc   # Note all resource values are in ns


#########################################
###   Equations FOR USER ADDED PINS   ###
#########################################

PINS DRAM0_VREFSSTL0
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS DRAM0_VREFSSTL1
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS DRAM0_VREFSSTL23
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS DRAM1_VREFSSTL0
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS DRAM1_VREFSSTL1
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS DRAM1_VREFSSTL23
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS USB20_XI
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS USB20_XO
r1 = 0.00 * Tcyc       		#  0.00 ns
r2 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS WDA_SYNC
d1 = 0.00 * Tcyc       		#  0.00 ns
d4 = 0.00 * Tcyc + Tcyc		#  0.00 ns

PINS RCLK0_IN
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 6.25ns
d4 = 0.35 * Tcyc + Tcyc
d5 = 0.85 * Tcyc + Tcyc

#PINS tg1I0
PINS XTAL_DISC TEST PCI_REQB[3] PCI_REQB[2] PCI_REQB[1]
d1 = 0.00 * Tcyc	# 0.00ns
d4 = 0.00 * Tcyc + Tcyc

#PINS tg1I1
PINS RESETB PCI_REQB[0]
#d1 = 0.58 * Tcyc	# 7.25ns
#d4 = 0.58 * Tcyc + Tcyc
d1 = 0.00 * Tcyc	# 7.25ns
d4 = 0.00 * Tcyc + Tcyc

#PINS tg1I2
PINS PCI_CLK
d1 = 0.35 * Tcyc	# 0.00ns
d2 = 0.85 * Tcyc	# 6.25ns
d4 = 0.35 * Tcyc + Tcyc
d5 = 0.85 * Tcyc + Tcyc

#PINS tg1B3
PINS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] PCI_AD[17] PCI_AD[16] PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] PCI_AD[7] PCI_AD[6] PCI_AD[5] PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] PCI_PAR PCI_TRDYB PCI_STOPB PCI_DEVSELB
d1 = 0.64 * Tcyc	# 8.25ns
d3 = 0.00 * Tcyc	# Tristate Edge
d4 = 0.64 * Tcyc + Tcyc 
d6 = 0.00 * Tcyc + Tcyc	# Tristate Edge
#r1 = 0.54 * Tcyc	# 6.75ns
#r2 = 0.54 * Tcyc + Tcyc
r1 = 0.80 * Tcyc	# 6.75ns
r2 = 0.80 * Tcyc + Tcyc

#PINS tg1B4
PINS PCI_CBEB[3] PCI_CBEB[1] PCI_CBEB[0] PCI_FRAMEB PCI_IRDYB
d1 = 0.64 * Tcyc	# 8.25ns
d3 = 0.00 * Tcyc	# Tristate Edge
d4 = 0.64 * Tcyc + Tcyc 
d6 = 0.00 * Tcyc + Tcyc	# Tristate Edge
r1 = 0.95 * Tcyc	# 11.88ns
r2 = 0.95 * Tcyc + Tcyc

#PINS tg1B5
PINS PCI_CBEB[2]
d1 = 0.64 * Tcyc	# 8.25ns
d3 = 0.00 * Tcyc	# Tristate Edge
d4 = 0.64 * Tcyc + Tcyc 
d6 = 0.00 * Tcyc + Tcyc	# Tristate Edge
r1 = 0.95 * Tcyc	# 11.88ns
r2 = 0.95 * Tcyc + Tcyc

#PINS tg1B6
PINS PCI_IDSEL[3] PCI_IDSEL[2] PCI_IDSEL[1] PCI_INTAB PCI_GNTB[3] PCI_GNTB[2] PCI_GNTB[1] PCI_GNTB[0] PB_AD[0] PB_AD[1] PB_AD[2] PB_AD[3] PB_AD[4] PB_AD[5] PB_AD[6] PB_AD[7] PB_AD[8] PB_AD[9] PB_AD[10] PB_AD[11] PB_AD[12] PB_AD[13] PB_AD[14] PB_AD[15] PB_A[0] PB_A[1] PB_A[2] PB_A[3] PB_A[4] PB_A[5] PB_A[6] PB_A[7] PB_A[8] PB_A[9] PB_A[10] PB_A[11] PB_A[12] PB_A[13] PB_A[14] PB_A[15] PB_A[16] PB_A[17] PB_A[18] PB_A[19] PB_A[20] PB_A[21] PB_A[22] PB_A[23] PB_A[24] PB_CSB[0] PB_CSB[1] PB_CSB[2] PB_CSB[3] PB_ALE PB_DIRB PB_DMACKB PB_DMARQ PB_IORDY PB_RDB PB_WRB
d1 = 0.00 * Tcyc	# 0.00ns
d3 = 0.00 * Tcyc	# Tristate Edge
d4 = 0.00 * Tcyc + Tcyc 
d6 = 0.00 * Tcyc + Tcyc	# Tristate Edge
#r1 = 0.55 * Tcyc	# 6.85ns
#r2 = 0.55 * Tcyc + Tcyc
r1 = 0.25 * Tcyc	# 6.85ns
r2 = 0.25 * Tcyc + Tcyc

#PINS tg1B7
PINS PCI_IDSEL[0]
#d1 = 0.67 * Tcyc	# 8.35ns
#d3 = 0.00 * Tcyc	# Tristate Edge
#d4 = 0.67 * Tcyc + Tcyc 
#d6 = 0.00 * Tcyc + Tcyc	# Tristate Edge
#r1 = 0.95 * Tcyc	# 11.88ns
#r2 = 0.95 * Tcyc + Tcyc
#
d1 = 0.00 * Tcyc	# 8.35ns
d3 = 0.00 * Tcyc	# Tristate Edge
d4 = 0.00 * Tcyc + Tcyc 
d6 = 0.00 * Tcyc + Tcyc	# Tristate Edge
r1 = 0.25 * Tcyc	# 11.88ns
r2 = 0.25 * Tcyc + Tcyc
@
EQSP TIM,SPS,#9000008565
##########################################################
#    Spec Set                                            #
##########################################################
EQNSET 1 "scan"


WAVETBL "scan"

CHECK all

SPECSET 1 "scan"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        45               45               90               [MHZ] 

EQNSET 2 "scanx3"

#
#
#
#
##########################################################
#    Spec Set scanx3                                     #
##########################################################
WAVETBL "scanx3"

CHECK all

SPECSET 1 "scanx3"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        40                                                 [MHZ] 

EQNSET 3 "bist"

#
#
#
##########################################################
#    Spec Set - bist                                     #
##########################################################
WAVETBL "bist"

CHECK all

SPECSET 1 "bist_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "bist"

CHECK all

SPECSET 2 "bist_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        65                                                 [MHZ] 

EQNSET 4 "serial_flash"

#
#
#
##########################################################
#    Spec Set serial_flash                               #
##########################################################
WAVETBL "serial_flash"

CHECK all

SPECSET 1 "serial_flash_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "serial_flash"

CHECK all

SPECSET 2 "serial_flash"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        65                                                 [MHZ] 

EQNSET 5 "dac"

#
#
#
##########################################################
#    Spec Set - bist                                     #
##########################################################
WAVETBL "dac"

CHECK all

SPECSET 1 "dac_setup1"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "dac"

CHECK all

SPECSET 2 "dac_setup2"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        70                                                 [MHZ] 


WAVETBL "dac"

CHECK all

SPECSET 3 "dac_capture"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        13.5                                               [MHZ] 

EQNSET 6 "pll"

#
#
#
##########################################################
#    Spec Set - bist                                     #
##########################################################
WAVETBL "pll"

CHECK all

SPECSET 1 "pll_setup1"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "pll"

CHECK all

SPECSET 2 "pll_setup2"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        70                                                 [MHZ] 


WAVETBL "pll"

CHECK all

SPECSET 3 "pll_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        70                                                 [MHZ] 

EQNSET 7 "serial_flash_bist"

#
#
#
##########################################################
#    Spec Set serial_flash_bist                          #
##########################################################
WAVETBL "serial_flash_bist"

CHECK all

SPECSET 1 "serial_flash_bist_skip"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "serial_flash_bist"

CHECK all

SPECSET 2 "serial_flash_bist"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        50                                                 [MHZ] 

EQNSET 8 "serialization"

#
#
#
##########################################################
#    Spec Set serialization                              #
##########################################################
WAVETBL "serialization"

CHECK all

SPECSET 1 "serialization_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "serialization"

CHECK all

SPECSET 2 "serialization"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        70                                                 [MHZ] 

EQNSET 9 "dram_bist"

#
#
#
##########################################################
#    Spec Set dram bist                                  #
##########################################################
WAVETBL "dram_bist"

CHECK all

SPECSET 1 "dram_bist_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "dram_bist"

CHECK all

SPECSET 2 "dram_bist_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        65                                                 [MHZ] 

EQNSET 12 "atspeed_bist_5us"

#
#
#
##########################################################
#    12/06/06 atspeed bist_5us                           #
#    - RCLK1_XTAL_IN on for 5us first                    #
#    - RCLK0_IN 1 = NRZ 1.                               #
#               0 = RZ                                   #
##########################################################
WAVETBL "atspeed_bist_5us"

CHECK all

SPECSET 1 "atspeed_bist_5us_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "atspeed_bist_5us"

CHECK all

SPECSET 2 "atspeed_bist_5us_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        80                                                 [MHZ] 

EQNSET 13 "display_func"

#
#
#
#
##########################################################
#    display_func  - Horizontal Noise test               #
##########################################################
WAVETBL "display_func"

CHECK all

SPECSET 1 "display_func_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "display_func"

CHECK all

SPECSET 2 "display_func_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        25                                                 [MHZ] 

EQNSET 14 "dram_func"

#
#
#
##########################################################
#    Spec Set                                            #
##########################################################
WAVETBL "dram_func"

CHECK all

SPECSET 1 "dram_func_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "dram_func"

CHECK all

SPECSET 2 "dram_func_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        65                                                 [MHZ] 

EQNSET 15 "serial_flash_x2"

#
##########################################################
#    Spec Set - serial flash 2x                          #
##########################################################
WAVETBL "serial_flash_x2"

CHECK all

SPECSET 1 "serial_flash_x2_setup"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        10                                                 [MHZ] 


WAVETBL "serial_flash_x2"

CHECK all

SPECSET 2 "serial_flash_x2_test"


# SPECNAME       *****ACTUAL***** *****MINIMUM**** *****MAXIMUM**** UNITS COMMENT
Frequency        65                                                 [MHZ] 
@
